LPC2921 datasheet(20/83 Pages) NXP

20 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

20 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

6.8.6 EEPROM

EEPROM is a non-volatile memory mostly used for storing relatively small amounts of

data, for example for storing settings. It contains one 16 kB memory block and is

byte-programmable and byte-erasable.

The EEPROM can be accessed only through the ﬂash controller.

6.9 General Purpose DMA (GPDMA) controller

The GPDMA controller allows peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the same AHB master or one area by each master.

The GPDMA controls eight DMA channels with hardware prioritization. The DMA

controller interfaces to the system via two AHB bus masters, each with a full 32-bit data

bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can

be either big-endian or little-endian. Incrementing or non-incrementing addressing for

source and destination are supported, as well as programmable DMA burst size. Scatter

or gather DMA is supported through the use of linked lists. This means that the source

and destination areas do not have to occupy contiguous areas of memory.

6.9.1 DMA support for peripherals

The GPDMA supports the following peripherals: SPI0/1/2 and UART0/1. The GPDMA can

access both embedded SRAM blocks, both TCMs, external static memory, and ﬂash

memory.

6.9.2 Clock description

The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see

Section 6.7.2.

6.10 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic

conﬁguration of the devices. All transactions are initiated by the Host controller.

The LPC2921/2923/2925 USB interface includes a device controller with on-chip PHY for

device. Details on typical USB interfacing solutions can be found in Section 10.2.

6.10.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfers data between the endpoint buffer and the on-chip

SRAM.

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