TMS320VC5421 datasheet(31/88 Pages) TI

31 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

direct memory access (DMA) controller (continued)

Program Page 0‡

McBSP

DXR/DRR

MMRegs Only

On-Chip

DARAM A

(32K Words)

Prog/Data

On-Chip

SARAM A

(32K Words)

Data Only

Hex

00 0000

00 001F

00 0020

00 005F

00 0060

00 7FFF

00 8000

00 FFFF

Program Page 1‡

On-Chip

Shared

DARAM 0

(32K Words)

Program

Only

On-Chip

Shared

DARAM 1

(32K Words)

Program

Only

Hex

01 0000

01 7FFF

01 8000

01 FFFF

Program Page 2‡

On-Chip

DARAM B

(32K Words)

Prog/Data

On-Chip

SARAM B

(32K Words)

Data Only

Hex

02 0000

02 7FFF

02 8000

02 FFFF

Program Page 3‡

On-Chip

Shared

DARAM 2

(32K Words)

Program

Only

On-Chip

Shared

DARAM 3

(32K Words)

Program

Only

Hex

03 0000

03 7FFF

03 8000

03 FFFF

02 005F

02 0060

McBSP

DXR/DRR

MMRegs Only

Subsystem A

Subsystem B

Shared 1

Shared 2

02 001F

02 0020

00 7FFF

00 8000

Hex

00 0000

00 FFFF

On-Chip

DARAM A/B

(32K Words)

Prog/Data

On-Chip

SARAM A/B

(32K Words)

Data Only

Data†

Shared 0

Shared 3

Subsystem A

Subsystem B

McBSP

DXR/DRR

MMRegs Only

00 001F

00 0020

00 005F

00 0060

Reserved

† DMD/DMS = 01

‡ DMD/DMS = 00

NOTES: A. All local memory is available to the DMA.

B. All I/O memory accesses by the DMA (DMD/DMS = 10) are mapped to the core-to-core FIFO.

C. In pages 00 and 02, in the range of 0020–005F, only the following memory mapped registers are accessible: 20,21,30,31,40,41

(read only), 22,23,32,33,42,43 (write only).

Figure 13. On-Chip Memory Map Relative to DMA (DLAXS/SLAXS = 0)

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