TMS320VC5421 datasheet(26/88 Pages) TI

26 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HPI nonmultiplexed mode

nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)

via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host

initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with

the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not

available in

nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA

read or write access. Figure 7 shows a block diagram of the HPI16 in

nonmultiplexed mode.

HOST

HPI-16

Data[15:0]

HD[15:0]

R/W

HR/W

Data strobes

HDS1, HDS2, HCS

HRDY

Ready

HPID[15:0]

DMA

’54x

CPU

Address[

n:0]

HA[n :0]

Figure 7. Interfacing to the HPI-16 in Non-Multiplexed Mode

other HPI16 system considerations

operation during IDLE

The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns

on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.

The DSP CPU does not wake up from the IDLE mode during this process.

downloading code during reset

The HPI16 can download code while the DSP is in reset. However, the system provides a pin (HPIRS) that

provides a way to take the HPI16 module out of reset while leaving the DSP in reset. The maximum HPI16 data

rate is 33 MBps assuming no other DMA activity (100-MIPS DSP subsystem).

emulation considerations

The HPI16 can continue operation even when the DSP CPU is halted due to debugger breakpoints or other

emulation events.

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