TMS320VC5421 datasheet(57/88 Pages) TI

57 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface timing for a memory write

switching characteristics over recommended operating conditions for a memory write

(MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 25)

PARAMETER

MIN

MAX

UNIT

td(CLKH-A)

Delay time, CLKOUT high to address valid‡

– 1

td(CLKL-A)

Delay time, CLKOUT low to address valid§

–1

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

–1

td(CLKL-D)W

Delay time, CLKOUT low to data valid

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

– 1

td(CLKH-RWL) Delay time, CLKOUT high to R/W low

td(CLKH-RWH) Delay time, CLKOUT high to R/W high

–1

td(RWL-MSTRBL) Delay time, R/W low to MSTRB low

H – 2

H + 2

th(A)W

Hold time, address valid after CLKOUT high‡

–1

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory write preceded by a memory write

§ In the case of a memory write preceded by an I/O cycle

timing requirements for a memory write (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 25)

MIN

MAX

UNIT

th(D)MSH

Hold time, write data valid after MSTRB high

H – 3

H +3§

tw(SL)MS

Pulse duration, MSTRB low§

4H–4

tsu(A)W

Setup time, address valid before MSTRB low

4H–4

tsu(D)MSH

Setup time, write data valid before MSTRB high

4H–5

4H+5§

† Address, PS, and DS timings are all included in timings referenced as address.

§ In the case of a memory write preceded by an I/O cycle

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