TMS320VC5421 datasheet(38/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

general-purpose I/O (continued)

GPIO2 is a special case where the logic level determines the operation of BIO-conditional instructions on the

CPU. GPIO2 is always mapped as a general-purpose I/O, but the BIO function exists when this pin is configured

as an input.

hardware timer

The ’54x devices feature a 16-bit timing circuit with a 4-bit prescaler. The timer counter decrements by one at

every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can

be stopped, restarted, reset, or disabled by specific status bits. The timer output pulse is driven on GPIO3 when

the TOUT bit is set to one in the general-purpose I/O control register. The device must be in HPI mode

(XIO = 0) to drive TOUT on the GPIO3 pin.

software-programmable phase-locked loop (PLL)

The clock generator provides clocks to the ’5421 device, and consists of a phase-locked loop (PLL) circuit. The

clock generator requires a reference clock input, which must be provided by using an external clock source. The

reference clock input is then divided by two (DIV mode) to generate clocks for the ’5421 device. Alternately, the

PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency

by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an

adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially

started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is

locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock

circuitry allows the synthesis of new clock frequencies for use as master clock for the ’5421 device. Only

subsystem A controls the PLL. Subsystem B cannot access the PLL registers.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in

software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using

the PLL circuitry.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

Figure 19 shows the bit layout of the clock mode register and Table 14 describes the bit functions.

PLLMUL†

PLLDIV†

PLLCOUNT†

PLLON/OFF†

PLLNDIV

STATUS

R/W

† When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.

LEGEND: R = Read, W = Write

Figure 19. Clock Mode Register (CLKMD)

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