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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5421 датащи(PDF) 37 Page - Texas Instruments |
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TMS320VC5421 датащи(HTML) 37 Page - Texas Instruments |
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37 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 general-purpose I/O In addition to the A_XF and B_XF pins, the ’5421 has eight general-purpose I/O pins. These pins are: A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3 B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3 Four general-purpose I/O pins are available to each core. Each GPIO pin can be individually selected as either an input or an output. Additionally, the timer output is selectable on GPIO pin 3. At core reset, all GPIO pins are configured as inputs. GPIO data and control bits are accessible through a memory-mapped register at 3Ch with the format shown in Figure 18. 15 14 13 12 11 10 987 6 5 43210 TOUT Reserved GPIO DIR3 GPIO DIR2 GPIO DIR1 GPIO DIR0 ROM EN CORE SEL XIO GRAN T XIO REQ GPIO DAT3 GPIO DAT2 GPIO DAT1 GPIO DAT0 R/W R/W R/W R/W R/W R/W R R R/W, R/W, R/W, R/W, R/W, +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 Note: R = Read, W = Write, +0 = Value at reset Figure 18. General-Purpose I/O Control Register Table 13. General-Purpose I/O Control Register Bit Functions BIT NO. BIT NAME BIT VALUE FUNCTION 15 TOUT 0 Timer output disable. Uses GPIO3 as general-purpose I/O. 15 TOUT 1 Timer output enable. Overrides DIR3. Timer output is driven on GPIO3 and readable in DAT3. 14-12 Reserved X Register bit is reserved. Read 0, write has no effect. 11 8 GPIO 0 GPIOn pin is used as an input. 11–8 GPIO DIRn† 1 GPIOn pin is used as an output. 7 ROMEN 0 ROM is mapped out 7 ROMEN 1 ROM is mapped in 6 CORE 0 cLEAD core A is selected for XIO REQ bit. DSP subsystem A is tied low internally for this bit. 6 CORE SEL 1 cLEAD core B is selected for XIO REQ bit. DSP subsystem B is tied high internally for this bit. 5 XIO 0 EMIF is not available to the cLEAD core determined by the CORE SEL bit. 5 XIO GRANT 1 EMIF is granted to the cLEAD core determined by the CORE SEL bit. 4 XIO 0 EMIF is not requested for the cLEAD core indicated by the CORE SEL bit. 4 XIO REQ 1 Request EMIF for the cLEAD core indicated by the CORE SEL bit. 30 GPIO 0 GPIOn is driven with a 0 (DIRn = 1). GPIOn is read as 0 (DIRn = 0). 3–0 GPIO DATn† 1 GPIOn is driven with a 1 (DIRn = 1). GPIOn is read as 1 (DIRn = 0). † n = 3, 2, 1, or 0 Register bit 7 is used as ROMEN to enable and disable ROM space. In XIO mode, ROM enable (ROMEN) reflects the state of the A_GPIO0 and B_GPIO0 pins (GPIODAT0 input) to enable the applicable on-chip ROM after reset. Register bits (6:4) are used for XIO arbitration of external memory interface (EMIF) control between DSP subsystems. The timer out (TOUT) bit is used to multiplex the output of the timer and GPIO3. All GPIO pins are programmable as an input or output by the direction bit (DIRn). Data is either driven or read from the data bit field (DATn). DIR3 has no affect when TOUT = 1. |
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