TMS320VC5421 datasheet(54/88 Pages) TI

54 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multiply-by-N clock option (PLL Enabled)

The frequency of the reference clock provided at the CLKIN pin can be multiplied by a factor of N to generate

the internal machine cycle. The selection of the clock mode and the value of N is described in the

software-programmable phase-locked loop (PLL) section.

switching

characteristics

over

recommended

operating

conditions

0.5tc(CO)]

(see Figure 23)

PARAMETER

’5421-200

UNIT

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

tc(CI)/N†

td(CI-CO)

Delay time, CLKIN high/low to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high

H–2

H–1

Transitory phase, PLL lock up time

† N = Multiplication factor

timing requirements (see Figure 23)†

’5421-200

UNIT

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1–15)

20‡

200

tc(CI)

Cycle time, CLKIN

PLL multiplier N = x.5

20‡

100

tc(CI)

Cycle time, CLKIN

PLL multiplier N = x.25, x.75

20‡

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

tw(CIL)

Pulse duration, CLKIN low

tw(CIH) Pulse duration, CLKIN high

† N = Multiplication factor

‡ The multiplication factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range

(tc(CO))

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

CLKIN

CLKOUT

td(CI-CO)

tw(COL)

tr(CI)

Unstable

tw(CIH)

tw(CIL)

Figure 23. External Multiply-by-One Clock Timing

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