TMS320VC5421 datasheet(53/88 Pages) TI

53 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

divide-by-two, divide-by-four, and bypass clock option (PLL Disabled)

The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in the software-programmable

phase-locked loop (PLL) section.

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 22,

and the recommended operating conditions table)

PARAMETER

’5421-200

UNIT

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

2tc(CI)

†

tc(CO)

Cycle time, CLKOUT – bypass mode

2tc(CI)

†

td(CIH-CO)

Delay time, CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high

H–2

H–1

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

timing requirements (see Figure 22)

’5421-200

UNIT

MIN

MAX

UNIT

tc(CI)

Cycle time, CLKIN

†

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

tw(CIL)

Pulse duration, CLKIN low

tw(CIH) Pulse duration, CLKIN high

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

tr(CO)

tf(CO)

CLKOUT

CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIH)

tw(CIL)

Figure 22. External Divide-by-Two Clock Timing

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