TMS320VC5421 datasheet(11/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Signal Descriptions (Continued)

NAME

DESCRIPTION

TYPE†

MEMORY CONTROL SIGNALS (CONTINUED)

READY

Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to

be completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY

again. The processor performs the READY detection if at least two software wait states are

programmed.

This pin is also multiplexed with the HPI, and functions as the host-port data ready (output) in HPI mode.

Refer to the HPI section of this table for details on the secondary function of this pin.

R/W

O/Z

Read/write output signal. R/W indicates transfer direction during communication to an external device.

R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write

operation.

This pin is also multiplexed with the HPI, and functions as the host-port read/write input in HPI mode.

Refer to the HPI section of this table for details on the secondary function of this pin.

This pin is placed into the high-impedance state when OFF is low.

IOSTRB

O/Z

I/O space memory strobe. External I/O space is accessible by the CPU and not the direct memory

access (DMA) controller. The DMA has its own dedicated I/O space that is not accessible by the CPU.

This pin is also multiplexed with the general-purpose I/O feature, and functions as the A_GPIO3

(A_TOUT) signal in HPI mode. Refer to the General Purpose I/O section of this table for details on the

secondary function of this pin.

This pin is placed into the high-impedance state when OFF is low.

PRIMARY

PPA18

O/Z

SELA/B

For HPI access (XIO=0), SELA/B is an input.

See Table 3 for a truth table of SELA/B, HMODE, and XIO pins and functionality.

For external memory accesses (XIO=1), SELA/B is multiplexed as output PPA18.

See the PPA signal descriptions. These pins are placed into the high-impedance

state when OFF is low.

HOLD‡

Hold. HOLD is asserted to request control of the address, data, and control lines. When

acknowledged, these lines go into the high-impedance state.

HOLDA

O/Z

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and

that the address, data, and control lines are in the high-impedance state, allowing them to be available

to the external circuitry. HOLDA also goes into the high-impedance state when OFF is low.

CLOCKING SIGNALS

A_CLKOUT

B_CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine

cycle is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1”

to the CLKOFF bit of the PMST register. CLKOUT goes into the high-impedance state when EMU1/OFF

is low.

CLKIN§

Input clock to the device. CLKIN connects to an oscillator circuit/device (PLL).

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins are Schmitt triggered inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

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