TMS320VC5421 datasheet(62/88 Pages) TI

номер детали	TMS320VC5421

подробное описание детали	DIGITAL SIGNAL PROCESSOR

PDF	88 Pages

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производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

(IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 29)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

–1

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

td(CLKH-D)IOW

Delay time, CLKOUT high to write data valid

H–5

H+3

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

–1

td(CLKL-RWL)

Delay time, CLKOUT low to R/W low

td(CLKL-RWH)

Delay time, CLKOUT low to R/W high

th(A)IOW

Hold time, address valid after CLKOUT low

–1

th(D)IOW

Hold time, write data after IOSTRB high

H–3

H+7

tsu(D)IOSTRBH

Setup time, write data before IOSTRB high

H–5

H+1

tsu(A)IOSTRBL

Setup time, address valid before IOSTRB low

H–3

H+3

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

PPD[15:0]

PPA[18:0]

CLKOUT

td(CLKH-ISTRBH)

th(A)IOW

th(D)IOW

td(CLKH-D)IOW

td(CLKH-ISTRBL)

td(CLKL-A)

td(CLKL-RWL)

td(CLKL-RWH)

tsu(A)IOSTRBL

tsu(D)IOSTRBH

Figure 29. Parallel I/O Port Write (IOSTRB=0)

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