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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5421 датащи(PDF) 59 Page - Texas Instruments |
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TMS320VC5421 датащи(HTML) 59 Page - Texas Instruments |
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59 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 59 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 26 and Figure 27) MIN MAX UNIT tsu(RDY) Setup time, READY before CLKOUT low 5 ns th(RDY) Hold time, READY after CLKOUT low 0 ns tv(RDY)MSTRB Valid time, READY after MSTRB low‡ 4H–8 ns th(RDY)MSTRB Hold time, READY after MSTRB low‡ 4H ns † The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states. ‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT MSTRB READY PPA[18:0] CLKOUT th(RDY) th(RDY)MSTRB tv(RDY)MSTRB Wait State Generated by READY Wait States Generated Internally tsu(RDY) Figure 26. Memory Read With Externally Generated Wait States |
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