TMS320VC5421 datasheet(19/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

data memory

The data memory space is a single page of 64K. Access is dependent on the address range. Access in the lower

32K of data memory is always from local DARAM.

Access in the upper 32K of data memory is dependent on the state of DROM.

D DROM = 0 – Data memory is accessed externally

D DROM = 1 – Data memory is accessed internally from local SARAM

I/O memory

The I/O space is a single page of 64K. Access is always external.

When XIO = 0 and an access to external memory is attempted, any write is ignored and any read is an unknown

value.

multicore reset signals

The ’5421 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function

as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the

CPU registers and upon release, initiate the reset function. Additionally, the A_RS signal resets the on-chip PLL

and initializes the CLKMD register to bypass mode.

The HPI reset signal (HPIRS) places the HPI peripheral into a reset state. It is necessary to wait three clock

cycles after the rising edge of HPIRS before performing an HPI access. The HPIRS signal also resets the PLL

by turning off the PLL and initializing the CLKMD register to bypass mode.

bootloader

The on-chip bootloader is used to automatically transfer user code from an external source to anywhere in

program memory after reset. The XIO pin is sampled during a hardware reset and the results indicate the

operating mode as shown in Table 2.

Table 2. Bootloader Operating Modes

XIO

AFTER RESET

HPI mode, bootload is controlled by host. The external host holds the ’5421 in reset while it loads the on-chip

memory of one or both subsystems as determined by the SELA/B pin.

The host can release the ’5421 from reset by either of the following methods:

If the RS_A/B pins are held low while HPIRS transitions from low to high, the subsystem cores reset will be

controlled by the RS_A/B pins. When the host has finished downloading code, it drives RS_A/B high to release

the cores from reset.

If the RS_A/B pins are held high while HPIRS transitions from low to high, the subsystems stay in reset until

a HPI data write to address 0x2F occurs. This means the host can download code to subsystem A and then

release core A from reset by writing any data to core A address 0x2F via the HPI. The host can then repeat

the sequence for core B. This mode allows the host to control the ’5421 reset without additional hardware.

XIO mode. ROM is mapped in, if ROMEN pin = 1 during reset.

The ’5421 bootloader provides the following options for the source of code to download:

D Parallel from 8-bit or 16-bit-wide EPROM

D Serial boot from McBSPs, 8-bit mode

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