TMS320VC5421 datasheet(75/88 Pages) TI

75 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0†

(see Figure 43)

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high

2 – 12H

th(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high

5 +12H

tsu(BFXL-BCKXH)

Setup time, BFSX low before BCLKX high

tc(BCKX)

Cycle time, BCLKX

12H

32H

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave:

[H=0.5tc(CO)] CLKSTP = 11b,

CLKXP = 0† (see Figure 43)

PARAMETER

MASTER‡

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low§

C – 5

C + 5

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high¶

T – 5

T + 5

td(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid

–2

6H + 4

10H + 19

tdis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from BCLKX

low

–2

6H + 4

10H + 17

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

D – 2

D +10

4H – 4

8H + 17

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ T = BCLKX period = (1 + CLKGDV) * 2H

C =

BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D =

BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

td(BFXL-BCKXH)

tdis(BCKXL-BDXHZ)

td(BCKXL-BDXV)

th(BCKXH-BDRV)

tsu(BDRV-BCKXH)

td(BFXL-BDXV)

th(BCKXL-BFXL)

LSB

MSB

tsu(BFXL-BCKXH)

tc(BCKX)

Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

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