TMS320VC5421 datasheet(70/88 Pages) TI

70 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing

timing requirements for the McBSP† [H=0.5tc(CO)] (see Figure 39 and Figure 40)

MIN

MAX

UNIT

tc(BCKRX)

Cycle time, BCLKR/X

BCLKR/X ext

tw(BCKRX)

Pulse duration, BCLKR/X low or BCLKR/X high

BCLKR/X ext

Hold time external BFSR high after BCLKR low

BCLKR int

th(BCKRL-BFRH)

Hold time, external BFSR high after BCLKR low

BCLKR ext

Hold time BDR valid after BCLKR low

BCLKR int

th(BCKRL-BDRV)

Hold time, BDR valid after BCLKR low

BCLKR ext

Hold time external BFSX high after BCLKX low

BCLKX int

th(BCKXL-BFXH)

Hold time, external BFSX high after BCLKX low

BCLKX ext

Setup time external BFSR high before BCLKR low

BCLKR int

tsu(BFRH-BCKRL)

Setup time, external BFSR high before BCLKR low

BCLKR ext

Setup time BDR valid before BCLKR low

BCLKR int

tsu(BDRV-BCKRL)

Setup time, BDR valid before BCLKR low

BCLKR ext

Setup time external BFSX high before BCLKX low

BCLKX int

tsu(BFXH-BCKXL)

Setup time, external BFSX high before BCLKX low

BCLKX ext

tr(BCKRX)

Rise time, BCLKR/X

BCLKR/X ext

tf(BCKRX)

Fall time, BCLKR/X

BCLKR/X ext

† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are

also inverted.

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