TMS320VC5421 datasheet(39/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

software-programmable phase-locked loop (PLL) (continued)

Table 14. Clock Mode Register (CLKMD) Bit Functions

BIT

NO.

BIT

NAME

FUNCTION

15–12

PLLMUL†

PLL multiplier. PLLMUL defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV. See Table 15.

PLL divider. PLLDIV defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV. See Table 15.

PLLDIV†

PLLDIV = 0

Means that an integer multiply factor is used

PLLDIV†

PLLDIV = 1

Means that a noninteger multiply factor is used

10–3

PLLCOUNT†

PLL counter value. PLLCOUNT specifies the number of input clock cycles (in increments of16 cycles) for the

PLL lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter

is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL

counter decrements by one.

The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid

clock signals are sent to the device.

PLLON/OFF†

PLL on/off. PLLON/OFF enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV

bit (see Table 16). Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when PLLON/OFF is high,

the PLL runs independently of the state of PLLNDIV.

PLLNDIV

PLLNDIV configures PLL mode when high or DIV mode when low. PLLNDIV defines the frequency multiplier in

conjunction with PLLDIV and PLLMUL. See Table 15.

Indicates the PLL mode.

STATUS

STATUS = 0

Indicates DIV mode

STATUS

STATUS = 1

Indicates PLL mode

† When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.

Table 15. Multiplier Related to PLLNDIV, PLLDIV, and PLLMUL

PLLNDIV

PLLDIV

PLLMUL

MULTIPLIER‡

0–14

0.5

0.25

0–14

PLLMUL + 1

bypass (multiply by 1)§

0 or even

(PLLMUL + 1)/2

odd

PLLMUL/4

‡ CLKOUT = CLKIN * Multiplier

§ Indicates the default clock mode after reset

Table 16. VCO Truth Table

PLLON/OFF

PLLNDIV

VCO STATE

off

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