TMS320VC5421 datasheet(55/88 Pages) TI

55 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface timing

switching characteristics over recommended operating conditions for a memory read

(MSTRB = 0)† (see Figure 24)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid‡

–1

td(CLKH-A)

Delay time, CLKOUT high (transition) to address valid§

–1

td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low

–1

td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high

– 1

th(CLKL-A)R Hold time, address valid after CLKOUT low‡

–1

4§

th(CLKH-A)R Hold time, address valid after CLKOUT high§

–1

4§

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory read preceded by a memory read

§ In the case of a memory read preceded by a memory write

timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 24)

MIN

MAX

UNIT

ta(A)M

Access time, read data access from address valid

ta(MSTRBL)

Access time, read data access from MSTRB low

tsu(D)R

Setup time, read data before CLKOUT low

th(D)R

Hold time, read data after CLKOUT low

th(A-D)R

Hold time, read data after address invalid

th(D)MSTRBH Hold time, read data after MSTRB high

† Address, PS, and DS timings are all included in timings referenced as address.

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