| поискавой системы для электроныых деталей |
|
TMP93CS44 датащи(PDF) 107 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP93CS44 датащи(HTML) 107 Page - Toshiba Semiconductor |
|
107 / 224 page ![]() TMP93CS44/S45 2004-02-10 93CS44-105 Timer 5 Mode Control Register 7 6 5 4 3 2 1 0 Bit symbol CAP3IN CAP34M1 CAP34M0 CLE T5CLK1 T5CLK0 T5MOD (0048H) Read/Write W R/W After reset 1 0 0 0 0 0 Function 0: Software capture 1: Don’t care Capture timing 00: Disable INT6 occurs at rising edge. 01: TI6 ↑ TI7 ↑ INT6 occurs at rising edge. 10: TI6 ↑ TI6 ↓ INT6 occurs at fall edge. 11: TFF1 ↑ TFF1↓ INT6 occurs at rising edge. 0: UC5 clear disable 1: UC5 clear enable Timer 5 source clock 00: TI6 pin 01: φT1 10: φT4 11: φT16 Figure 3.8.5 16-Bit Timer/Event Counter Related Register (3/6) Timer 5 input clock 00 External clock (TI6) 01 φT1 10 φT4 11 φT16 Clearing the up counter UC5 0 Clear disable 1 Clear by match with TREG7 Timer 5 capture timing Capture control INT6 Control 00 Capture disable 01 CAP3 at TI6 rise CAP4 at TI7 rise Interrupt occurs at the rising edge of TI6 (INT6) input. 10 CAP3 at TI6 rise CAP4 at TI6 fall Interrupt occurs at the falling edge of TI6 (INT6) input. 11 CAP3 at TFF1 rise CAP4 at TFF1 fall Interrupt occurs at the rising edge of TI6 (INT6) input. Software capture control 0 The up counter 5 value is loaded to CAP3. 1 Don’t care |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |