 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
TMP93CS41 датащи(PDF) 229 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP93CS41 датащи(HTML) 229 Page - Toshiba Semiconductor |
|
|
229 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-227 Timer control (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 FF3C1 FF3C0 FF3TRG1 FF3TRG0 FF2C1 FF2C0 FF2TRG1 FF2TRG0 W R/W W R/W 1 1 0 0 1 1 0 0 PFFCR PWM flip-flop control 2AH 00: Don’t care 01: Set TFF3 10: Clear TFF3 11: Don’t care 00: Prohibit TFF3 invert 01: Invert if matched 10: Set if matched; clear if overflow 11: Clear if matched; set if overflow 00: Don’t care 01: Set TFF2 10: Clear TFF2 11: Don’t care 00: Prohibit TFF2 invert 01: Invert if matched 10: Set if matched; clear if overflow 11: Clear if matched; set if overflow − W TREG4L 16-bit timer register 4 low 30H (Prohibit RMW) Undefined − W TREG4H 16-bit timer register 4 high 31H (Prohibit RMW) Undefined − W TREG5L 16-bit timer register 5 low 32H (Prohibit RMW) Undefined − W TREG5H 16-bit timer register 5 high 33H (Prohibit RMW) Undefined − R CAP1L Capture register 1 low 34H Undefined − R CAP1H Capture register 1 high 35H Undefined − R CAP2L Capture register 2 low 36H Undefined − R CAP2H Capture register 2 high 37H Undefined CAP2T5 EQ5T5 CAP1IN CAP12M1 CAP12M0 CLE T4CLK1 T4CLK0 R/W W R/W 0 0 1 0 0 0 0 0 TFF5 INV TRG 0: TRG disable 1: TRG enable T4MOD 16-bit timer 4 source CLK and mode 38H Inverted when the UC value is latched to CAP2 Inverted when the up counter matches TREG5 0: Soft- ware capture 1: Don’t care Capture timing 00: Disable 01: T14 ↑ T15 ↑ 10: T14 ↑ T14 ↓ 11: TFF1 ↑ TFF1 ↓ 1: UC4 clear enable Source clock 00: T14 01: φT1 10: φT4 11: φT16 TFF5C1 TFF5C0 CAP2T4 CAP1T4 EQ5T4 EQ4T4 TFF4C1 TFF4C0 W R/W W 1 1 0 0 0 0 1 1 TFF4 invert trigger 0: Trigger disable 1: Trigger enable T4FFCR 16-bit timer 4 flip-flop control 39H 00: Invert TFF5 01: Set TFF5 10: Clear TFF5 11: Don’t care Inverted when the UC value is latched to CAP2 Inverted when the UC value is latched to CAP1 Inverted when the UC value matches TREG5 Inverted when the UC value matches TREG4 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 11: Don’t care |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
