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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 232 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 232 Page - Toshiba Semiconductor |
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232 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-230 (6) Serial channel Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 R (Receiving)/W (Transmission) SC0BUF Serial channel 0 buffer 50H Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Cleared to 0 by reading) R/W Undefined 0 0 0 0 0 0 0 1: Error SC0CR Serial channel 0 control 51H Receiving data bit8 Parity 0: Odd 1: Even 1: Parity enable Overrun Parity Framing 0: SCLK0 1: SCLK0 1: Input SCLK0 pin TB8 CTSE RXE WU SM1 SM0 SC1 SC0 R/W Undefined 0 0 0 0 0 0 0 SC0MOD Serial channel 0 mode 52H Transmission data bit8 1: CTS enable 1: Receive enable 1: Wake up enable 00: I/O Interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 00: TO0 trigger 01: Baud rate generator 10: Internal clock φ1 11: Don’t care − BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R/W R/W 0 0 0 0 0 0 0 BR0CR Baud rate control 53H Always fixed to 0 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0 to F (“1” prohibited) RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 R (Receiving)/W (Transmission) SC1BUF Serial channel 1 buffer 54H Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Cleared to 0 by reading) R/W Undefined 0 0 0 0 0 0 0 1: Error SC1CR Serial channel 1 control 55H Receiving data bit8 Parity 0: Odd 1: Even 1: Parity enable Overrun Parity Framing 0:SCLK1 1: SCLK1 1: Input SCLK1 pin TB8 − RXE WU SM1 SM0 SC1 SC0 R/W 0 0 0 0 0 0 0 0 SC1MOD Serial channel 1 mode 56H Transmission data bit8 Always fixed to 0 1: Receive enable 1: Wake up enable 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 00: TO0 Trigger 01: Baud rate generator 10: Internal clock φ1 11: Don’t care − BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R/W R/W 0 0 0 0 0 0 0 BR1CR Baud rate control 57H Always fixed to 0 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0 to F (“1” prohibited) ODE1 ODE0 R/W 0 0 ODE Serial open- drain enable 58H 1: P93 Open drain 1: P90 Open drain |
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