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TMP93CS41 датащи(PDF) 159 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 159 Page - Toshiba Semiconductor |
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159 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-157 7 6 5 4 3 2 1 0 Bit symbol PG03 PG02 PG01 PG00 SA03 SA02 SA01 SA00 Read/Write W R/W After reset 0 0 0 0 Undefined Function Pattern generation 0 (PG0) output latch register PG0 can be read by reading the port (P6) that is assigned to PG Shift alternate register 0 for the PG mode (4-bit write) register Figure 3.10.4 Pattern generation 0 register (PG0REG) 7 6 5 4 3 2 1 0 Bit symbol PG13 PG12 PG11 PG10 SA13 SA12 SA11 SA10 Read/Write W R/W After reset 0 0 0 0 Undefined Function Pattern generation 1 (PG1) output latch register PG1 can be read by reading the port (P6) that is assigned to PG Shift alternate register 1 for the PG mode (4-bit write) register Figure 3.10.5 Pattern Generation 1 Register (PG1REG) PG0REG (004CH) PG1REG (004DH) Prohibit read- modify- write Prohibit read- modify- write |
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