AM62A7 datasheet(213/238 Pages) TI1

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8.5.7 Error Signaling Module (ESM)

The Error Signaling Module (ESM) aggregates events and/or errors from throughout the device into one location.

It can signal both low and high priority interrupts to a processor to deal with an event and/or manipulate an I/O

error pin to signal an external hardware that an error has occurred. Therefore an external controller is able to

reset the device or keep the system in a safe, known state.

For more information, see Error Signaling Module section in Peripherals chapter in the device TRM.

8.5.8 Enhanced Quadrature Encoder Pulse (EQEP)

The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary

incremental encoder to get position, direction and speed information from a rotating machine for use in high

performance motion and position control system. The disk of an incremental encoder is patterned with a single

track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is

defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second

track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used

to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as

index, marker, home position and zero reference.

For more information, see Enhanced Quadrature Encoder Pulse section in Peripherals chapter in the device

TRM.

8.5.9 General-Purpose Interface (GPIO)

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be

configured as either inputs or outputs. When configured as an output, user can write to an internal register

to control the state driven on the output pin. When configured as an input, user can obtain the state of the input

by reading the state of an internal register.

In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different

interrupt/event generation modes.

For more information, see General-Purpose Interface section in Peripherals chapter in the device TRM.

8.5.10 General-Purpose Memory Controller (GPMC)

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external

memory devices like:

• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

• NAND flash

• Pseudo-SRAM devices

For more information, see General-Purpose Memory Controller section in Peripherals chapter in the device

TRM.

8.5.11 Global Timebase Counter (GTC)

The GTC module provides a continuous running counter that can be used for time synchronization and debug

trace time stamping.

For more information, see Global Timebase Counter section in Peripherals chapter in the device TRM.

8.5.12 Inter-Integrated Circuit (I2C)

The device contains multicontroller Inter-Integrated Circuit (I2C) controllers each of which provides an interface

between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial

bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and

from the LH device through the 2-wire I2C interface.

Each multicontroller I2C module can be configured to act like a target or controller I2C-compatible device.

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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