AM62A7 datasheet(210/238 Pages) TI1

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8.4 Other Subsystems

8.4.1 Dual Clock Comparator (DCC)

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.

The desired accuracy can be programed based on calculation for each application. The DCC measures the

frequency of a selectable clock source using another input clock as a reference.

For more information, see Dual Clock Comparator section in Peripherals chapter in the device TRM.

8.4.2 Data Movement Subsystem (DMSS)

The DMSS module provides data movement (DMA) and bridges between the CBA switched interconnect and

the packet streaming fabric (network on chip) on the device.

The Data Movement Subsystem (DMSS) consists of DMA/Queue Management components and Peripherals:

• Packet DMA

• Block Copy DMA

• Ring Accelerator

• Packet Streaming Interface (PSILSS)

• Infrastructure components such as CBASS, secure proxy, and an interrupt aggregator

8.4.3 Memory Cyclic Redundancy Check (MCRC)

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the

integrity of a memory system. A signature representing the contents of the memory is obtained when the

contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate

the signature for a set of data and then compare the calculated signature value against a pre-determined good

signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in

parallel and can be used on any memory system.

For more information, see Memory Cyclic Redundancy Check section in Peripherals chapter in the device TRM.

8.4.4 Peripheral DMA Controller (PDMA)

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs

of peripherals, which perform data transfers using memory mapped registers (MMRs) accessed via a standard

non-coherent bus fabric. The PDMA module is located close to one or more peripherals which require an

external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting

only statically configured transfer request (TR) operations.

The PDMA is only responsible for performing the data movement transactions which interact with the peripherals

themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data

stream which is then sent to a remote peer DMSS destination channel which then performs the movement of the

data into memory. Likewise, a remote DMSS source channel fetches data from memory and transfers it to a peer

PDMA destination channel over PSI-L which then performs the writes to the peripheral.

The PDMA architecture is intentionally heterogeneous (DMSS + PDMA) to right size the data transfer complexity

at each point in the system to match the requirements of whatever is being transferred to or from. Peripherals

are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO dimensioning

requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically for sample

size and FIFO depth), hardcoded address maps, and simple triggering capabilities.

Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous

transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and

employs round-robin scheduling between channels in order to share the underlying DMA hardware.

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

www.ti.com

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