AM62A7 datasheet(209/238 Pages) TI1

209 / 238 page

8.3 Accelerators and Coprocessors

8.3.1 C7xV-256 Deep Learning Accelerator

Single Core C7x/MMA subsystem with 32KB Instruction cache and 64KB data cache

8.3.2 Vision Pre-processing Accelerator

The Vision Pre-processing Accelerator (VPAC) subsystem is a set of common vision primitive functions,

performing pixel data processing tasks, such as: color processing and enhancement, noise filtering, wide

dynamic range (WDR) processing, lens distortion correction, pixel remap for de-warping, on-the-fly scale

generation, on-the-fly pyramid generation. The VPAC offloads these common tasks from the main SoC

processors (ARM, DSP, etc.), so these CPUs can be utilized for differentiated high-lelvel algorithms. The

VPAC is designed to support multiple cameras by working in time-multiplexing mode. The VPAC also includes

an imaging pipe, which can be integrated on-the-fly with external camera sensor, as well as does memory-to-

memory (M2M) processing on pixel data

The VPAC subsystem provides 4 processing blocks: Vision Imaging Sub-System (VISS), Lens Distortion

Correction (LDC), Multi-Scalar (MSC) and Noise Filter (NF), along with Hardware Thread Scheduler (HTS),

Load Store Engin (LSE), and 512 KB of internal L2 memory.

For more information, see Vision Pre-processing Accelerator (VPAC) section in Processors and Accelerators

chapter in the device TRM.

8.3.3 JPEG Encoder

The JPEG Encoder is a scalable performance still image encoder. It supports the JPEG baseline still image

encode. The source is raw picture data and the output is the fully constructed compressed image. The JPEG

Encoder receives the image source through the memory interface (via MMU). It supports 4:2:2 and 4:2:0 YCbCr

picture formats. As a coprocessor, the host processor needs only to manage the higher level control code

functions such as providing the image to encode and choosing compression settings.

For more information, see JPEG Encoder section in Processors and Accelerators chapter in the device TRM.

8.3.4 Video Accelerator

The Video Accelerator is a 4K codec that supports both HEVC and H.264/AVC video formats. It provides high

performance encode and decode capability up to 8bit 4K@60fps with a single-core architecture.

The Video Accelerator can encode and/or decode any resolution up to 8192 x 4320. It guarantees real-time

performance for encoding/decoding 4K 60fps based on its sophisticated, latency tolerant hardware architecture.

The Video Accelerator is highly optimized for memory bandwidth loading and excellent power management.

The Video Accelerator contains a 32-bit processor called V-CPU, which is responsible for parsing bitstream

syntax in decoder orencoding bitstream syntax in encoder from sequence to slice header unit, pre-scanning

slice data, controlling the underlying video hardware blocks called V-CORE. The V-CPU also communicates with

host CPU through host register interface. The V-CORE performs actual processing of coded slice data: entropy

decoding, inverse scan, inverse transform/quantization, motion compensation, and loop filtering in decoder and

motion estimation, intra prediction, RDO, and entropy coding in encoder. This software and hardware combined

architecture can provide flexibility and high throughput at the same time.

For more information, see Video Accelerator section in Processors and Accelerators chapter in the device TRM.

www.ti.com

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

Submit Document Feedback

209

Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1

AM62A7 датащи(PDF) 209 Page - Texas Instruments

AM62A7 датащи(HTML) 209 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL