AM62A7 datasheet(2/238 Pages) TI1

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Functional Safety:

• Functional Safety-Compliant targeted [Industrial]

– Developed for functional safety applications

– Documentation will be available to aid IEC

61508 functional safety system design

– Systematic capability up to SIL 3 targeted

– Hardware Integrity up to SIL 2 targeted

– Safety-related certification

• IEC 61508 by TÜV SÜD planned

• Functional Safety-Compliant targeted [Automotive]

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Systematic capability up to ASIL D targeted

– Hardware integrity up to ASIL B targeted

– Safety-related certification

• ISO 26262 by TÜV SÜD planned

• AEC - Q100 qualified [Automotive]

Security:

• Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Trusted Execution Environment (TEE) supported

– Arm TrustZone® based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

• Dedicated Security Controller with user

programmable HSM core and dedicated security

DMA & IPC subsystem for isolated processing

• Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

• Supports cryptographic cores

– AES – 128-/192-/256-Bit key sizes

– SHA2 – 224-/256-/384-/512-Bit key sizes

– DRBG with true random number generator

– PKA (Public Key Accelerator) to Assist in

RSA/ECC processing for secure boot

• Debugging security

– Secure software controlled debug access

– Security aware debugging

High-Speed Interfaces:

• Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time Sensitive Networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

• Two USB2.0 Ports

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

General Connectivity:

• 9x Universal Asynchronous Receiver-Transmitters

(UART)

• 5x Serial Peripheral Interface (SPI) controllers

• 6x Inter-Integrated Circuit (I2C) ports

• 3x Multichannel Audio Serial Ports (McASP)

– Transmit and Receive Clocks up to 50 MHz

– Up to 16/10/6 Serial Data Pins across 3x

McASP with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and Similar Formats

– Supports Digital Audio Interface Transmission

(SPDIF, IEC60958-1, and AES-3 Formats)

– FIFO Buffers for Transmit and Receive (256

Bytes)

– Support for audio reference output clock

• 3x enhanced PWM modules (ePWM)

• 3x enhanced Quadrature Encoder Pulse modules

(eQEP)

• 3x enhanced Capture modules (eCAP)

• General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

• 3x Controller Area Network (CAN) modules with

CAN-FD support

– Conforms w/ CAN Protocol 2.0 A, B and ISO

11898-1

– Full CAN FD support (up to 64 data bytes)

– Parity/ECC check for Message RAM

– Speed up to 8 Mbps

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

www.ti.com

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