AM62A7 datasheet(95/238 Pages) TI1

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(10) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and

VDDA_DDR_PLL0 when not using Partial IO low power mode.

VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or

0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior to VDDR_CORE as defined by this waveform.

(11) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDD_CORE, VDDA_CORE_CSIRX0,

VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.

VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or

0.85V. When these supplies are operating at 0.85V, they shall be powered from the same source as VDDR_CORE and ramped during

the 0.85V ramp period defined by this waveform.

(12) The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or

power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at

0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE.

VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is

operating at 0.85V.

(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and

during normal device operation. This supply shall only be sourced while programming eFuse.

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1

AM62A7 датащи(PDF) 95 Page - Texas Instruments