AM62A7 datasheet(94/238 Pages) TI1

94 / 238 page

7.10.2.2.1 Power-Up Sequencing

Table 7-4 and Figure 7-5 describes the device power-up sequencing.

Note

The power supply sequencing requirements defined in this section does not include entry or exit

from low power modes. See Section 7.10.2.2.3, Partial IO Power Sequencing for more information on

power supply sequence requirements when entering or exiting low power modes.

Table 7-4. Power-Up Sequencing – Supply / Signal Assignments

See: Figure 7-5

WAVEFORM

SUPPLY / SIGNAL NAME

VSYS(1), VMON_VSYS(2)

VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB,

VMON_3P3_SOC(4)

VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDA_MCU,

VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_PLL3, VDDA_PLL4, VDDA_PLL5,

VDDA_1P8_CSIRX0, VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2, VMON_1P8_SOC(6)

VDDSHV4(7), VDDSHV5(7), VDDSHV6(7)

VDDS_DDR(8), VDDS_DDR_C(8)

VDD_CANUART(9)

VDD_CANUART(10), VDD_CORE(10) (12), VDDA_CORE_CSIRX0(10), VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10)

VDD_CANUART(11), VDD_CORE(11) (12), VDDA_CORE_CSIRX0(11), VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11),

VDDR_CORE(12)

VPP(13)

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XI

(1)

VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply

that sources power management devices which source all other supplies.

(2)

VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see the System Power

Supply Monitor Design Guidelines.

(3)

VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V

depending on the application requirements.

VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any

valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power

source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.

When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V

supplies during the 3.3V ramp period defined by this waveform.

(4)

The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V supply source.

(5)

VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V

depending on the application requirements.

VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any

valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power

source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.

When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V

supplies during the 1.8V ramp period defined by this waveform.

(6)

The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V supply source.

(7)

VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any

dependency on other power rails. This capability is required to support UHS-I SD Cards.

(8)

VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.

(9)

VDD_CANUART shall be connected to an always-on power source when using Partial IO low power mode.

When VDD_CANUART is connected to an always-on power source, the potential applied to VDD_CORE must never be greater than

the potential applied to VDD_CANUART + 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before

and ramp down after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for VDD_CORE.

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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