AM62A7 datasheet(73/238 Pages) TI1

73 / 238 page

6.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements

and unused package balls.

Note

All power pins must be supplied with the voltages specified in Section 7.4, Recommended Operating

Conditions, unless otherwise specified.

Note

For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be

connected to these device ball numbers.

Table 6-71. Connectivity Requirements

AMB

BALL

NUMBER

BALL NAME

CONNECTION REQUIREMENTS

F15

MCU_ERRORn

TRSTn

Each of these balls must be connected to VSS through separate external pull

resistors to ensure the inputs associated with these balls are held to a valid

logic low level if a PCB signal trace is connected and not actively driven by an

attached device. The internal pull-down can be used to hold a valid logic low

level if no PCB signal trace is connected to the ball.

C13

E10

C12

E19

A14

A16

B14

EMU0

EMU1

MCU_RESETz

RESET_REQz

TCK

TDI

TMS

Each of these balls must be connected to the corresponding power supply(1)

through separate external pull resistors to ensure the inputs associated with

these balls are held to a valid logic high level if a PCB signal trace is connected

and not actively driven by an attached device. The internal pull-up can be used

to hold a valid logic high level if no PCB signal trace is connected to the ball.

E12

D13

E13

MCU_I2C0_SCL

MCU_I2C0_SDA

WKUP_I2C0_SCL

WKUP_I2C0_SDA

Each of these balls must be connected to the corresponding power supply(1)

through separate external pull resistors to ensure the inputs associated with

these balls are held to a valid logic high level.

N21

N20

N19

N18

N17

P18

P19

P21

P22

R19

R20

R22

T22

R21

T20

T21

GPMC0_AD0

GPMC0_AD1

GPMC0_AD2

GPMC0_AD3

GPMC0_AD4

GPMC0_AD5

GPMC0_AD6

GPMC0_AD7

GPMC0_AD8

GPMC0_AD9

GPMC0_AD10

GPMC0_AD11

GPMC0_AD12

GPMC0_AD13

GPMC0_AD14

GPMC0_AD15

Each of these balls must be connected to the corresponding power supply(1)

or VSS through separate external pull resistors to ensure the inputs associated

with these balls are held to a valid logic high or low level as appropriate to

select the desired device boot mode.

AA1

AB2

VDDS_DDR

VDDS_DDR_C

If DDRSS is not used, each of these balls must be connected directly to VSS.

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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