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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM62A7 датащи(PDF) 49 Page - Texas Instruments |
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AM62A7 датащи(HTML) 49 Page - Texas Instruments |
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49 / 238 page  Table 6-6. CPTS Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] CP_GEMAC_CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output from CPSW3G0 CPTS C16, D22 CP_GEMAC_CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output from CPSW3G0 CPTS A17, C22 CP_GEMAC_CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B15, D21 CP_GEMAC_CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B22, E15 SYNC0_OUT O CPTS Time Stamp Generator Bit 0 Output from Time Sync Router D17 SYNC1_OUT O CPTS Time Stamp Generator Bit 1 Output from Time Sync Router B16 SYNC2_OUT O CPTS Time Stamp Generator Bit 2 Output from Time Sync Router B17 SYNC3_OUT O CPTS Time Stamp Generator Bit 3 Output from Time Sync Router C18 6.3.3 CSI-2 6.3.3.1 MAIN Domain Table 6-7. CSIRX0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] CSI0_RXCLKN I CSI Differential Receive Clock Input (negative) AB14 CSI0_RXCLKP I CSI Differential Receive Clock Input (positive) AB13 CSI0_RXRCALIB (1) A CSI pin connected to external resistor for on-chip resistor calibration V10 CSI0_RXN0 I CSI Differential Receive Input (negative) W12 CSI0_RXN1 I CSI Differential Receive Input (negative) Y13 CSI0_RXN2 I CSI Differential Receive Input (negative) AA13 CSI0_RXN3 I CSI Differential Receive Input (negative) AB11 CSI0_RXP0 I CSI Differential Receive Input (positive) W13 CSI0_RXP1 I CSI Differential Receive Input (positive) Y14 CSI0_RXP2 I CSI Differential Receive Input (positive) AA12 CSI0_RXP3 I CSI Differential Receive Input (positive) AB10 (1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is 7.2mW. No external voltage should be applied to this pin. 6.3.4 DDRSS 6.3.4.1 MAIN Domain Table 6-8. DDRSS0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] DDR0_ACT_n O DDRSS Activation Command N5 DDR0_ALERT_n IO DDRSS Alert H7 DDR0_CAS_n (1) O DDR4 Column Address Strobe / LPDDR4 Chip Select 1B M5 DDR0_PAR O DDRSS Command and Address Parity N2 DDR0_RAS_n (1) O DDR4 Row Address Strobe / LPDDR4 Chip Select 0B M6 DDR0_WE_n O DDRSS Write Enable N6 DDR0_A0 O DDRSS Address Bus J5 DDR0_A1 O DDRSS Address Bus J2 www.ti.com AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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