AM62A7 datasheet(83/238 Pages) TI1

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Table 7-2. Device Operating Performance Points

OPP

A53SS(1)

C7x

FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)

MT/s(3)

MAIN

SYSCLK

MCU

R5F

SYSCLK

DEVICE

MANAGER

R5F

CLK

HSM

VPAC

VENC

VDEC

MJPEG

LPDDR4

High

From

ARM0

PLL

Bypass

Speed

Grade

Maximum

From

C7x

PLL

Bypass

Speed

Grade

Maximum

500

800

400

800

400

187.5,

375

400,

200,

100

250

From

DDR

PLL

Bypass(4)

Speed

Grade

Maximum

Low

250

400

200

400

133

(1)

Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.

(2)

Fixed operating frequency, set by software at boot.

(3)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

(4)

The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL

Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.

7.6 Power Consumption Summary

For information on the device power consumption, see the AM62Ax Power Estimation Tool application note.

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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