AM62A7 datasheet(8/238 Pages) TI1

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• (DSS Switching Characteristics): Added external pixel clock mode "EXTPCLKIN" to parameters D2, D3, D4,

and D5. Also changed the "Internal PLL" mode min value for parameters D2 and D3 from "0.0475P" to

"0.0475P - 0.3"............................................................................................................................................... 127

• (MCASP): Updated each AHCLKR/X table note to include a TRM reference for clock source options. Also

corrected a typographical error on the signal name associated with the first waveform in each timing diagram

by changing "MCASP[x]_ACLKR/X" to "MCASP[x]_AHCLKR/X"...................................................................159

• (MCSPI Switching Characteristics - Controller Mode): Replaced previous table notes 2 and 3 with new table

notes 2, 3, 4, and 5.........................................................................................................................................164

• (MMC0 DLL Delay Mapping): Changed the OTAPDLYENA and OTAPDLYSEL values for Legacy SDR and

High Speed SDR modes................................................................................................................................ 170

• (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Changed the "UHS-I DR50" mode name to "UHS-I

DDR50" to correct a typographical error.........................................................................................................182

• (OSPI0 Timing Requirements – PHY Data Training): Added three new timing parameters. Two that define

timing parameters associated with SRD with External Board Loopback, and one that defines the minimum

input data valid window for each mode. Also updated Note 1 to clarify the purpose of the new data valid

window parameter.......................................................................................................................................... 192

• (OSPI0 Timing Requirements – PHY Data Training, SDR with External Board Loopback): Added a new timing

requirements diagram for SDR with External Board Loopback...................................................................... 192

• (OSPI Switching Characteristics – PHY Data Training): Added seven new timing parameters. Six that define

timing parameters associated with SRD with External Board Loopback, and one that defines the maximum

output data valid window for each mode........................................................................................................ 192

• (OSPI Switching Characteristics – PHY Data Training): Added maximum values to the OSPI0_CLK Cycle

Time parameters (O1) and (07) to define a minimum operating frequency of 100MHz. Updated Note 1 and

Note 4, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed

to "reference clock" in Note 4 so it matches the clock name used in the TRM. Also updated Note 6 to clarify

the purpose of the new data invalid window parameter................................................................................. 192

• (OSPI0 Switching Characteristics – PHY SDR Data Training): Added a new switching characteristics diagram

for SDR with External Board Loopback.......................................................................................................... 192

• (OSPI0 Switching Characteristics – PHY SDR Mode): Updated Note 1 and Note 4, where "in ns" was added

to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it

matches the clock name used in the TRM..................................................................................................... 196

• (OSPI0 Switching Characteristics – PHY DDR Mode): Updated Note 1 and Note 4, where "in ns" was added

to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it

matches the clock name used in the TRM..................................................................................................... 198

• (OSPI0 Timing Requirements – Tap SDR Mode): Updated the constant values associated with the minimum

setup and minimum hold formulas in parameters O19 and O20. Note 2 was also updated to change "refclk" to

"reference clock" so it matches the clock name used in the TRM..................................................................200

• (OSPI0 Switching Characteristics – Tap SDR Mode): Updated Note 1 and Note 4, where "in ns" was added to

the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it

matches the clock name used in the TRM..................................................................................................... 200

• (OSPI0 Timing Requirements – Tap DDR Mode): Updated the constant values associated with the minimum

setup and minimum hold formulas in parameters O13 and O14. Note 2 was also updated to change "refclk" to

"reference clock" so it matches the clock name used in the TRM..................................................................202

• (OSPI0 Switching Characteristics – Tap DDR Mode): Updated the minimum data output delay and maximum

data output delay formulas in parameter O6. Also updated Note 1 and Note 5, where "in ns" was added to the

OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 5 so it

matches the clock name used in the TRM..................................................................................................... 202

• (Detailed Description): Added content to "Detailed Description" section and associated subsections.......... 207

• (Power Supply Designs): Added new section with link to PMIC application note...........................................216

• (Clock Routing Guidelines): Added new section............................................................................................ 224

• (Standard Package Symbolization): Updated image to match updates applied to the Nomenclature

Description table in the Device Naming Convention section.......................................................................... 226

• (Device Naming Convention): Changed "Q" to "Q1" and "ppp" to "PPP" in the FIELD PARAMETER column so

they match the Standard Package Symbolization figure................................................................................ 227

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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