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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM62A7 датащи(PDF) 12 Page - Texas Instruments |
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AM62A7 датащи(HTML) 12 Page - Texas Instruments |
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12 / 238 page  6 Terminal Configuration and Functions 6.1 Pin Diagrams Note The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 6-1 shows the ball locations for the 484-ball flip chip ball grid array (FCBGA) package to quickly locate signal names and ball grid numbering. This figure is used in conjunction with Section 6.2.1 through Section 6.4 (Pin Attributes table and all Signal Descriptions tables, including the Pin Connectivity Requirements table). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AB AA Y W V U T R P N M L K J H G F E D C B A Not to scale VSS VDDS_DDR VSS DDR0_DQ31 VSS MMC0_DAT1 MMC0_CLK MMC0_DAT7 VSS CSI0_RXP3 CSI0_RXN3 VSS CSI0 _RXCLKP CSI0 _RXCLKN VSS RGMII1 _RD0 RGMII1 _TXC VSS RGMII2 _TXC RGMII2 _RD3 RGMII2 _RD2 VSS VDDS_DDR VSS DDR0_DQ29 VSS DDR0_DQ30 MMC0_DAT0 MMC0_DAT3 VSS USB0_DP USB0_DM VSS CSI0_RXP2 CSI0_RXN2 VSS RGMII1_RX _CTL RGMII1 _RXC RGMII1 _TD3 RGMII2 _TD2 RGMII2 _TD0 RGMII2 _RXC RGMII2 _RD0 VOUT0 _PCLK DDR0_DQS3 _n DDR0_DQ24 VSS DDR0_DQ28 VSS MMC0_CMD MMC0_DAT2 MMC0_DAT4 VSS USB1_DP USB1_DM VSS CSI0_RXN1 CSI0_RXP1 VSS RGMII1 _TD2 RGMII1 _TD0 RGMII2 _TD1 RGMII2_TX _CTL RGMII2 _RD1 VOUT0 _DATA14 VOUT0 _DATA15 DDR0_DQS3 VSS DDR0_DM3 VSS DDR0_DQ27 VSS MMC0_DAT5 VSS MMC0_DAT6 USB0 _RCALIB VSS CSI0_RXN0 CSI0_RXP0 VSS RGMII1 _RD2 RGMII1_TX _CTL RGMII2 _TD3 RGMII2_RX _CTL VOUT0 _DATA13 VOUT0 _DATA12 VOUT0 _DATA11 VOUT0 _DATA10 VSS DDR0_DQ25 VSS DDR0_DQ26 VSS USB1_VBUS VSS USB0_VBUS VSS CSI0 _RXRCALIB RSVD7 MDIO0_MDC MDIO0 _MDIO RGMII1 _RD3 RGMII1 _RD1 RGMII1 _TD1 VOUT0 _VSYNC VOUT0 _DATA9 VOUT0 _DATA8 VSS VOUT0 _DATA7 VOUT0 _DATA6 DDR0_DM2 VSS DDR0_DQ23 VSS DDR0_DQ18 VSS USB1 _RCALIB VDDSHV4 VSS VDDA_3P3 _USB RSVD6 VSS VDDSHV2 VSS VDD_CORE VSS VOUT0_DE VOUT0 _DATA5 VOUT0 _DATA3 VOUT0 _DATA2 VOUT0 _DATA1 VOUT0 _DATA0 VSS DDR0_DQ22 VSS DDR0_DQ17 VSS DDR0_DQ16 VSS VDDSHV4 VDDA_CORE _USB VDDA_1P8 _USB VDDA_CORE _CSIRX0 VDDA_1P8 _CSIRX0 VDDSHV2 CAP_VDDS2 VSS VDD_CORE VSS VOUT0 _HSYNC VOUT0 _DATA4 GPMC0 _AD14 GPMC0 _AD15 GPMC0 _AD12 DDR0_DQS2 VSS DDR0_DQ21 VSS DDR0_DQ19 VSS DDR0_BG1 CAP_VDDS4 VDD_CORE VSS VDDA_PLL1 VSS VDDSHV2 VSS VDD_CORE VSS GPMC0 _WAIT1 GPMC0 _WAIT0 GPMC0_AD9 GPMC0 _AD10 GPMC0 _AD13 GPMC0 _AD11 DDR0_DQS2 _n DDR0_DQ20 DDR0_CKE0 DDR0_BG0 DDR0_CKE1 DDR0 _RESET0_n VSS VDDS_DDR VDDR_CORE VDD_CORE VSS VDDR_CORE VSS VDD_CORE VSS VDDA _TEMP0 VSS GPMC0_AD5 GPMC0_AD6 VSS GPMC0_AD7 GPMC0_AD8 VSS DDR0_PAR DDR0_ODT1 DDR0_CS1 _n DDR0_ACT _n DDR0_WE_n VDDS_DDR VSS VDDA_PLL0 VSS VDD_CORE VSS VDD_CORE VSS VDDSHV3 VSS GPMC0_AD4 GPMC0_AD3 GPMC0_AD2 GPMC0_AD1 GPMC0_AD0 GPMC0_CLK DDR0_CK0 DDR0_A13 DDR0_A12 VSS DDR0_CAS _n DDR0_RAS _n VSS VDDS_DDR VDDA_DDR _PLL0 VDDR_CORE VSS VDD_CORE VDDA_PLL2 VDDR_CORE VDDSHV3 CAP_VDDS3 VSS GPMC0 _BE1n GPMC0 _CSn0 GPMC0 _CSn3 GPMC0 _CSn1 GPMC0 _CSn2 DDR0_CK0 _n DDR0_A9 VSS DDR0_A3 DDR0_A11 DDR0_A8 VDDS_DDR VDDS_DDR _C VDD_CORE VDDA _TEMP2 VDD_CORE VSS VDD_CORE VSS VDDSHV3 VDDSHV1 GPMC0_OEn _REn GPMC0 _ADVn_ALE GPMC0 _BE0n_CLE VSS OSPI0_DQS OSPI0_CLK VSS DDR0_A10 DDR0_A6 VSS DDR0_A5 DDR0_BA0 VSS VDDS_DDR VSS VDDA_PLL4 VSS VDDR_CORE VDDA_PLL3 VDD_CORE VDDSHV1 CAP_VDDS1 GPMC0_WPn GPMC0_DIR GPMC0_WEn OSPI0 _CSn2 OSPI0_D4 OSPI0 _LBCLKO DDR0_A4 DDR0_A1 VSS DDR0_A2 DDR0_A0 DDR0_CS0 _n VDDS_DDR VDDS_OSC0 VDD_CORE VDDA_MCU VDD_CORE VSS VDD_CORE VDDR_CORE VDD_CORE CAP_VDDS6 VSS OSPI0_D1 OSPI0_D2 OSPI0_D6 OSPI0_D0 OSPI0_D7 VSS DDR0_A7 DDR0_BA1 VSS DDR0_ODT0 DDR0_CAL0 DDR0 _ALERT_n VDDSHV _CANUART VDD _CANUART VDDSHV _MCU VSS VMON_VSYS VDDSHV0 VSS VDDSHV5 VDDSHV6 VDDSHV6 OSPI0_D3 OSPI0_D5 VSS OSPI0 _CSn0 MMC2_CLK DDR0_DQS1 DDR0_DQ11 VSS DDR0_DQ13 VSS DDR0_DQ12 RSVD5 CAP_VDDS _CANUART VSS CAP_VDDS _MCU VDDSHV _MCU VSS CAP_VDDS0 VDDSHV0 CAP_VDDS5 VDDSHV5 VSS VDDA _TEMP1 OSPI0 _CSn1 OSPI0 _CSn3 MMC2_DAT3 MMC2_CMD DDR0_DQS1 _n VSS DDR0_DM1 VSS DDR0_DQ9 RSVD3 VPP MCU_UART0 _TXD VMON_3P3 _SOC RSVD4 VSS VMON_1P8 _SOC VSS UART0 _CTSn TRSTn VSS EXTINTn PORz_OUT RESETSTA Tz MMC2_DAT2 MMC2_DAT1 MMC2_SDCD VSS DDR0_DQ8 VSS DDR0_DQ14 VSS DDR0_DQ10 RSVD2 MCU_MCAN0 _RX WKUP _UART0 _TXD EMU1 MCU_SPI0 _CS0 MCU_I2C0 _SCL WKUP_I2C0 _SDA UART0_RXD SPI0_D1 I2C0_SDA I2C1_SDA MMC1_SDCD RESET _REQz MMC2_DAT0 MMC2_SDWP MMC1_CLK DDR0_DQS0 VSS DDR0_DQ15 VSS DDR0_DQ3 RSVD1 MCU_MCAN1 _TX MCU_UART0 _RXD MCU_I2C0 _SDA MCU_UART0 _RTSn VSS PMIC_LPM _EN0 WKUP_I2C0 _SCL MCU_RESETS TATz UART0_TXD SPI0_CS0 I2C0_SCL MMC1_SDWP USB1 _DRVVBUS VSS MMC1_DAT1 MMC1_DAT3 DDR0_DQS0 _n DDR0_DM0 DDR0_DQ5 VSS DDR0_DQ4 RSVD0 MCU_MCAN0 _TX WKUP _UART0 _RTSn WKUP _UART0 _RXD WKUP _UART0 _CTSn MCU_SPI0 _CS1 MCU _RESETz EMU0 TDO UART0 _RTSn SPI0_CS1 I2C1_SCL MCAN0_RX MCASP0 _AXR3 USB0 _DRVVBUS MMC1_CMD MMC1_DAT2 VDDS_DDR DDR0_DQ6 VSS DDR0_DQ1 VSS DDR0_DQ2 VSS MCU _ERRORn MCU_MCAN1 _RX WKUP _CLKOUT0 MCU_UART0 _CTSn MCU_SPI0 _D1 MCU_SPI0 _CLK TMS SPI0_D0 EXT _REFCLK1 MCAN0_TX MCASP0 _AXR1 MCASP0 _AXR2 MCASP0 _AXR0 MCASP0 _AFSR MMC1_DAT0 VSS VDDS_DDR DDR0_DQ7 VSS DDR0_DQ0 VSS MCU_PORz WKUP _LFOSC0 _XI WKUP _LFOSC0 _XO VSS MCU_OSC0 _XO MCU_OSC0 _XI VSS TCK MCU_SPI0 _D0 TDI SPI0_CLK VSS MCASP0 _ACLKX MCASP0 _AFSX MCASP0 _ACLKR VSS Figure 6-1. AMB FCBGA-N484 Pin Diagram (Bottom View) AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 www.ti.com 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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