LXT971ABC datasheet(5/90 Pages) INTEL

5 / 90 page

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

Figures

LXT971A Block Diagram...................................................................................................9

64-Pin PBGA Pin Assignments.........................................................................................10

64-Pin LQFP Pin Assignments..........................................................................................11

Management Interface Read Frame Structure...................................................................21

Management Interface Write Frame Structure ..................................................................21

Interrupt Logic...................................................................................................................22

Initialization Sequence ......................................................................................................24

Hardware Configuration Settings ......................................................................................26

Link Establishment Overview ...........................................................................................28

10BASE-T Clocking .........................................................................................................30

100BASE-X Clocking .......................................................................................................30

Link Down Clock Transition.............................................................................................30

Loopback Paths .................................................................................................................31

100BASE-X Frame Format...............................................................................................32

100BASE-TX Data Path....................................................................................................33

100BASE-TX Reception with no Errors...........................................................................33

100BASE-TX Reception with Invalid Symbol .................................................................33

100BASE-TX Transmission with no Errors......................................................................34

100BASE-TX Transmission with Collision......................................................................34

Protocol Sublayers.............................................................................................................35

LED Pulse Stretching ........................................................................................................42

Typical Twisted-Pair Interface - Switch............................................................................45

Typical Twisted-Pair Interface - NIC................................................................................46

Typical MII Interface ........................................................................................................47

Typical Fiber Interface ......................................................................................................48

100BASE-TX Receive Timing - 4B Mode .......................................................................53

100BASE-TX Transmit Timing - 4B Mode......................................................................54

100BASE-FX Receive Timing..........................................................................................55

100BASE-FX Transmit Timing ........................................................................................56

10BASE-T Receive Timing ..............................................................................................57

10BASE-T Transmit Timing.............................................................................................58

10BASE-T Jabber and Unjabber Timing ..........................................................................59

10BASE-T SQE (Heartbeat) Timing.................................................................................59

Auto Negotiation and Fast Link Pulse Timing..................................................................60

Fast Link Pulse Timing .....................................................................................................60

MDIO Input Timing ..........................................................................................................61

MDIO Output Timing........................................................................................................61

Power-Up Timing..............................................................................................................62

RESET Pulse Width and Recovery Timing ......................................................................62

PHY Identifier Bit Mapping..............................................................................................68

PBGA Package Specification ............................................................................................79

LXT971A LQFP Package Specifications..........................................................................80

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