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LXT971ABC датащи(PDF) 81 Page - Intel Corporation

номер детали LXT971ABC
подробное описание детали  3.3V Dual-Speed Fast Ethernet PHY Transceiver
PDF  90 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

LXT971ABC датащи(HTML) 81 Page - Intel Corporation

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
81
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 52. Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type 1
Default
16.15
Reserved
Write as zero, ignore on read.
R/W
0
16.14
Force Link Pass
1 = Force Link pass
0 = Normal operation
R/W
0
16.13
Transmit Disable
1 = Disable Twisted Pair transmitter
0 = Normal Operation
R/W
0
16.12
Bypass Scrambler
(100BASE-TX)
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
R/W
0
16.11
Reserved
Ignore
R/W
0
16.10
Jabber
(10BASE-T)
1 = Disable Jabber Correction
0 = Normal operation
R/W
0
16.9
SQE
(10BASE-T)
1 = Enable Heart Beat
0 = Disable Heart Beat
R/W
0
16.8
TP Loopback
(10BASE-T)
1 = Disable TP loopback during half-duplex
operation
0 = Normal Operation
R/W
0
16.7
CRS Select
(10BASE-T)
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
R/W
1
16.6
Sleep Mode
1 = Enable Sleep Mode
0 = Disable Sleep Mode
R/W
Note 2
16.5
PRE_EN
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
CRS is asserted.
R/W
0
16.4:3
Sleep Timer
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
R/W
00
16.2
Fault Code
Enable
1 = Enable FEFI transmission
0 = Disable FEFI transmission
R/W
1
16.1
Alternate NP
feature
1 = Enable alternate auto negotiate next page
feature.
0 = Disable alternate auto negotiate next page
feature
R/W
0
16.0
Fiber Select
1 = Select fiber mode.
0 = Select TP mode.
R/W
Note 3
1. R/W = Read /Write
LHR = Latches High on Reset
2. The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7.
3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP).



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