LXT971ABC datasheet(33/90 Pages) INTEL

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.6.2

Transmit Enable

The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN

after the last bit of the packet.

3.6.3

Receive Data Valid

The LXT971A asserts RX_DV when it receives a valid packet. Timing changes depend on line

operating speed:

• For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble

of the data packet.

• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the

Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.

3.6.4

Carrier Sense

Carrier Sense (CRS) is an asynchronous output. It is always generated when a packet is received

from the line and in half-duplex mode when a packet is transmitted. Table 10 summarizes the

conditions for assertion of carrier sense, collision, and data loopback signals.

Carrier sense is not generated when a packet is transmitted and in full-duplex mode.

3.6.5

Error Signals

When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts

RX_ER and drives “1110” on the RXD pins.

When the MAC asserts TX_ER, the LXT971A drives “H” symbols out on the TPFOP/N pins.

3.6.6

Collision

The LXT971A asserts its collision signal, asynchronously to any clock, whenever the line state is

half-duplex and the transmitter and receiver are active at the same time. Table 10 summarizes the

conditions for assertion of carrier sense, collision, and data loopback signals.

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