LXT971ABC datasheet(18/90 Pages) INTEL

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

Table 4. LXT971A Miscellaneous Signal Descriptions

PBGA

Pin#

LQFP

Pin#

Symbol

Type1

Signal Description

TxSLEW0

TxSLEW1

Tx Output Slew Controls 0 and 1. These pins select the TX

output slew rate (rise and fall time) as follows:

TxSLEW1

TxSLEW0

Slew Rate (Rise and Fall Time)

3.0 ns

3.4 ns

3.9 ns

4.4 ns

RESET

Reset. This active Low input is OR’ed with the control

cycle is extended to 258

µs (nominal) after reset is de-

asserted.

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

Address <4:0>. Sets device address.

RBIAS

Bias. This pin provides bias current for the internal circuitry.

Must be tied to ground through a 22.1 k

Ω, 1% resistor.

PAUSE

Pause. When set High, the LXT971A advertises Pause

capabilities during auto-negotiation.

SLEEP

Sleep. When set High, this pin enables the LXT971A to go

into a low-power sleep mode. The value of this pin can be

overridden by Register bit 16.6 when in managed mode.

PWRDWN

Power Down. When set High, this pin puts the LXT971A in a

power-down mode.

REFCLK/XI

Crystal Input and Output. A 25 MHz crystal oscillator circuit

can be connected across XI and XO. A clock can also be

used at XI. Refer to “Clock Requirements” on page 26 in the

Functional Description section.

B7, C7

9, 10

N/C

No Connection. These pins are not used and should not be

terminated.

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.

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