LXT971ABC datasheet(22/90 Pages) INTEL

22 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.2

Network Media / Protocol Support

The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or

100 Mbps Ethernet over fiber media (100BASE-FX).

3.2.1

10/100 Network Interface

The network interface port consists of five external pins (two differential signal pairs and a signal

detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. Refer to Figure 3 on page

13 for specific pin assignments.

The LXT971A output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.

When not transmitting data, the LXT971A generates 802.3-compliant link pulses or idle code.

Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending

on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine

the speed of this interface.

3.2.1.1

Twisted-Pair Interface

The LXT971A supports either 100BASE-TX or 10BASE-T connections over 100

Ω, Category 5,

Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT971A continuously

transmits and receives MLT3 symbols. When not transmitting data, the LXT971A generates

“IDLE” symbols.

During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being

exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link

up.

Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete

this interface. On the transmit side, the LXT971A has an active internal termination and does not

require external termination resistors. Intel's patented waveshaping technology shapes the outgoing

signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on

page 18) allow the designer to match the output waveform to the magnetic characteristics. On the

receive side, the internal impedance is high enough that it has no practical effect on the external

termination circuit.

3.2.1.2

Fiber Interface

The LXT971A fiber port is designed to interface with common industry-standard fiber modules. It

incorporates a Low Voltage PECL interface that complies with the ANSI X3.166 standard for

seamless integration.

Fiber mode is selected through Register bit 16.0 by the following two methods:

1. Drive the SD input to a value greater than 600 mV during power-up and reset states (all

LVPECL signaling levels from a fiber transceiver are acceptable).

2. Configure Register bit 16.0 = 1 through the MDIO interface.

LXT971ABC датащи(PDF) 22 Page - Intel Corporation

LXT971ABC датащи(HTML) 22 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL