LXT971ABC datasheet(24/90 Pages) INTEL

24 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO

interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a

higher drive strength.

3.2.3

Configuration Management Interface

The LXT971A provides both an MDIO interface and a Hardware Control Interface for device

configuration and management.

3.2.3.1

MDIO Management Interface

The LXT971A supports the IEEE 802.3 MII Management Interface also known as the

Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to

monitor and control the state of the LXT971A. The MDIO interface consists of a physical

connection, a specific protocol that runs across the connection, and an internal set of addressable

registers.

Some registers are required and their functions are defined by the IEEE 802.3 standard. The

LXT971A also supports additional registers for expanded functionality. The LXT971A supports

multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using

an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).

The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this

interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write

operations are disabled and the Hardware Control Interface provides primary configuration control.

When MDDIS is Low, the MDIO port is enabled for both read and write operations and the

Hardware Control Interface is not used.

3.2.3.1.1 MDIO Addressing

The protocol allows one controller to communicate with multiple LXT971A chips. Pins

ADDR<4:0> determine the chip address.

3.2.3.1.2 MDIO Frame Structure

The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is

shown in Figures 4 and 5 (read and write). MDIO Interface timing is shown in Table 38 on

page 69.

Figure 4. Management Interface Read Frame Structure

MDC

MDIO

(Read)

32 "1"s

0110

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Write

Read

D15

D14

Idle

High Z

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