LXT971ABC datasheet(17/90 Pages) INTEL

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

MII Control Interface Pins

MDDIS

Management Disable. When MDDIS is High, the MDIO is disabled

from read and write operations.

When MDDIS is Low at power-up or reset, the Hardware Control

Interface pins control only the initial or “default” values of their

respective register bits. After the power-up/reset cycle is complete,

bit control reverts to the MDIO serial channel.

MDC

Management Data Clock. Clock for the MDIO serial data channel.

Maximum frequency is 8 MHz.

MDIO

I/O

Management Data Input/Output. Bidirectional serial data channel

for PHY/STA communication.

MDINT

Management Data Interrupt. When Register bit 18.1 = 1, an active

Low output on this pin indicates status change. Interrupt is cleared

by reading Register 19.

Table 3. LXT971A Network Interface Signal Descriptions

PBGA

Pin#

LQFP

Pin#

Symbol

Type1

Signal Description

TPFOP

TPFON

Twisted-Pair/Fiber Outputs, Positive & Negative.

During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive

802.3 compliant pulses onto the line.

During 100BASE-FX operation, TPFOP/N pins produce differential

LVPECL outputs for fiber transceivers.

TPFIP

TPFIN

Twisted-Pair/Fiber Inputs, Positive & Negative.

During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive

differential 100BASE-TX or 10BASE-T signals from the line.

During 100BASE-FX operation, TPFIP/N pins receive differential

LVPECL inputs from fiber transceivers.

SD/TP

Signal Detect2: Dual function input depending on the state of the

device.

Reset and Power-Up. Media mode selection:

Tie High for FX mode (Register bit 16.0 = 1)

Tie Low for TP mode (Register bit 16.0 = 0)

Normal Operation (FX Mode): SD input from the fiber transceiver.

Normal Operation (TP Mode): Tie to GND (uses an internal pull-

down).

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

2. For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an

LVPECL logic High (2.4 V).

Table 2. LXT971A MII Signal Descriptions (Continued)

PBGA

Pin#

LQFP

Pin#

Symbol

Type1

Signal Description

1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain

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