LXT971ABC datasheet(35/90 Pages) INTEL

номер детали	LXT971ABC

подробное описание детали	3.3V Dual-Speed Fast Ethernet PHY Transceiver

PDF	90 Pages

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производитель	INTEL [Intel Corporation]

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.6.7.1

Operational Loopback

Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data

transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData).

Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.

3.6.7.2

Test Loopback

A test loopback function is provided for diagnostic testing of the LXT971A. During test loopback,

twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped

back by the LXT971A and returned to the MAC.

Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by

setting the following register bits:

• Register bit 0.14 = 1

• Register bit 0.8 = 1 (full-duplex)

• Register bit 0.12 = 0 (disable auto-negotiation).

Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is enabled

by setting Register bit 0.14 = 1 and tying the SD input to an LVPECL logic High value (2.4 V).

Figure 13. Loopback Paths

10T

Loopback

Digital

Block

MII

TX Driver

100X

Loopback

FX Driver

Analog

Block

LXT971A

LXT971ABC датащи(PDF) 35 Page - Intel Corporation