AD9161BBCZ datasheet(15/144 Pages) AD

15 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 15 of 144

Pin No.

Mnemonic

Description

G6, G7, G9, G10

VDD12_DCD/DLL

1.2 V Digital Supply Voltage.

G15

Serial Port Chip Select Bar (Active Low) Input. CMOS

levels on this pin are determined with respect to

IOVDD.

H14

SDO

Serial Port Data Output. CMOS levels on this pin are

determined with respect to IOVDD.

J13

SCLK

Serial Port Data Clock. CMOS levels on this pin are

determined with respect to IOVDD.

K13

SDIO

Serial Port Data Input/Output. CMOS levels on this pin

are determined with respect to IOVDD.

RESET

Reset Bar (Active Low) Input. CMOS levels on this pin

are determined with respect to IOVDD.

TX_ENABLE

Transmit Enable Input. This pin can be used instead of

the DAC output bias power down bits in Register 0x040,

Bits [1:0] to enable the DAC output. CMOS levels are

determined with respect to IOVDD.

P5, P11

DNC

Do Not Connect. Do not connect to these pins.

J2, J14, K2, K14, M2, M14, N2, N14, P3, P4, P6, P7, P9, P10,

P12, P13

VDD_1P2

1.2 V SERDES Digital Supply.

IOVDD

Supply Voltage for CMOS Input/Output and SPI.

Operational for 1.8 V to 3.3 V plus tolerance (see Table 1

for details).

K6, K7, K8, K9, K10

DVDD

1.2 V Digital Supply Voltage.

L3, L13

DVDD_1P2

1.2 V SERDES Digital Supply Voltage.

M3, M13

VTT_1P2

1.2 V SERDES VTT Digital Supply Voltage.

J1, K1

SERDIN7+,

SERDIN7−

SERDES Lane 7 Positive and Negative Inputs.

M1, N1

SERDIN6+,

SERDIN6−

SERDES Lane 6 Positive and Negative Inputs.

R3, R4

SERDIN5+,

SERDIN5−

SERDES Lane 5 Positive and Negative Inputs.

R6, R7

SERDIN4+,

SERDIN4-

SERDES Lane 4 Positive and Negative Inputs.

R9, R10

SERDIN3−,

SERDIN3+

SERDES Lane 3 Negative and Positive Inputs.

R12, R13

SERDIN2−,

SERDIN2+

SERDES Lane 2 Negative and Positive Inputs.

M15, N15

SERDIN1+,

SERDIN1−

SERDES Lane 1 Positive and Negative Inputs.

J15, K15

SERDIN0+,

SERDIN0−

SERDES Lane 0 Positive and Negative Inputs.

N4, N5

SYSREF+, SYSREF−

System Reference Positive and Negative Inputs. These

pins are self biased for ac coupling. They can be

ac-coupled or dc-coupled.

PLL_CLK_VDD12

1.2 V SERDES Phase-Locked Loop (PLL) Clock Supply

Voltage.

PLL_LDO_VDD12

1.2 V SERDES PLL Supply.

N11, N12

SYNCOUT−,

SYNCOUT+

Negative and Positive LVDS Sync (Active Low) Output

Signals.

P2, P14

SYNC_VDD_3P3

3.3 V SERDES Sync Supply Voltage.

PLL_LDO_BYPASS

1.2 V SERDES PLL Supply Voltage Bypass.

R1, R15

BIAS_VDD_1P2

1.2 V SERDES Supply Voltage.

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