AD9161BBCZ datasheet(83/144 Pages) AD

83 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 83 of 144

R/W

Value

Description

0x111

Configure the datapath options for Bit 7 (INVSINC_EN), Bit 6 (NCO_EN), Bit 4 (FILT_BW), Bit 2

(MODULUS_EN), Bit 1 (SEL_SIDEBAND), and Bit 0 (FIR85_FILT_EN). See the Register Summary section for

details on the options. Set the reserved bits (Bit 5 and Bit 3) to 0b0.

0x230

Configure the CDR block according to Table 20 for both half rate enable and the divider.

0x289,

Bits[1:0]

Set up the SERDES PLL divider based on the conditions shown in Table 19.

0x084,

Bits[5:4]

Set up the PLL reference clock rate based on the conditions shown in Table 19.

0x200

0x00

Enable JESD204B block (disable master SERDES power-down).

0x475

0x09

Soft reset the JESD204B quad-byte deframer.

0x453, Bit 7

0b1

(Optional) Enable scrambling on SERDES lanes.

0x458,

Bits[7:5]

Set the subclass type: 0b000 = Subclass 0, 0b001 = Subclass 1.

0x459,

Bits[7:5]

0b1

Set the JESD204x version to JESD204B.

0x45D

Program the calculated checksum value for Lane 0 from values in Register 0x450 to Register 0x45C.

0x475

0x01

Bring the JESD204B quad-byte deframer out of reset.

0x201,

Bits[7:0]

Set any bits to 1 to power down the appropriate physical lane.

0x2A7

0x01

(Optional) Calibrate SERDES PHY Termination Block 1 (PHY 0, PHY 1, PHY 6, PHY 7).

0x2AE

0x01

(Optional) Calibrate SERDES PHY Termination Block 2 (PHY 2, PHY 3, PHY 4, PHY 5).

0x29E

0x1F

Override defaults in the SERDES PLL settings (private).

0x206

0x00

Reset the CDR.

0x206

0x01

Enable the CDR.

0x280

0x01

Enable the SERDES PLL.

0x281, Bit 0

0b1

Read back Register 0x281 until Bit 0 = 1 to indicate the SERDES PLL is locked. Prior to enabling the links, be

sure that the JESD204B transmitter is enabled and ready to begin bringing up the link.

0x300

0x01

Enable SERDES links (begin bringing up the link).

0x470

0xFF

Read the CGS status for all lanes.

0x471

0xFF

Read the frame sync status for all lanes.

0x472

0xFF

Read the good checksum status for all lanes.

0x473

0xFF

Read the initial lane sync status for all lanes.

0x024

0x1F

Clear the interrupts.

0x4BA

0xFF

Clear the SERDES interrupts.

0x4BB

0x01

Clear the SERDES interrupt.

Table 44. Configure NCO Sequence

R/W

Value

Description

0x110

0x80

(Optional) Perform this write if NCO only mode is desired (AD9162 only).

0x111, Bit 6

0b1

Configure NCO_EN (Bit 6) = 0b1. Configure other datapath options for Bit 7 (INVSINC_EN), Bit 4 (FILT_BW),

Bit 2 (MODULUS_EN), Bit 1 (SEL_SIDEBAND), and Bit 0 (FIR85_FILT_EN). See the Register Summary section

for details on the options. Set the reserved bits (Bit 5 and Bit 3) to 0b0.

0x150, Bit 1

Configure the DC_TEST_EN bit: 0b0 = NCO operation with data interface; 0b1 = NCO only mode (AD9162 only).

0x14E

Write the amplitude value for tone amplitude in NCO only mode, Bits [15:8] (AD9162 only).

0x14F

Write the amplitude value for tone amplitude in NCO only mode, Bits [7:0] (AD9162 only).

0x113

0x00

Ensure the frequency tuning word write request is low.

0x119

Write FTW, Bits[47:40].

0x118

Write FTW, Bits[39:32].

0x117

Write FTW, Bits[31:24].

0x116

Write FTW, Bits[23:16].

0x115

Write FTW, Bits[15:8].

0x114

Write FTW, Bits[7:0].

0x113

0x01

Load the FTW to the NCO.

AD9161BBCZ датащи(PDF) 83 Page - Analog Devices

AD9161BBCZ датащи(HTML) 83 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL