AD9161BBCZ datasheet(76/144 Pages) AD

76 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 76 of 76

When considering the trace width vs. copper weight and

thickness, the speed of the interface must be considered. At

multigigabit speeds, the skin effect of the conducting material

confines the current flow to the surface. Maximize the surface

area of the conductor by making the trace width made wider to

reduce the losses. Additionally, loosely couple differential traces

to accommodate the wider trace widths. This coupling helps

reduce the crosstalk and minimize the impedance mismatch

when the traces must separate to accommodate components,

vias, connectors, or other routing obstacles. Tightly coupled vs.

loosely coupled differential traces are shown in Figure 178.

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELY COUPLED

DIFFERENTIAL Tx LINES

Figure 178. Tightly Coupled vs. Loosely Coupled Differential Traces

AC Coupling Capacitors

The AD9161/AD9162 require that the JESD204B input signals

be ac-coupled to the source. These capacitors must be 100 nF

and placed as close as possible to the transmitting logic device.

To minimize the impedance mismatch at the pads, select the

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

SYNCOUT±, SYSREF±, and CLK± Signals

The SYNCOUT± and SYSREF± signals on the AD9161/AD9162

are low speed LVDS differential signals. Use controlled impedance

traces routed with 100 Ω differential impedance and 50 Ω to

ground when routing these signals. As with the SERDIN0± to

SERDIN7± data pairs, it is important to keep these signals sepa-

rated from potential noise sources such as high speed digital

signals and noisy supplies.

Separate the SYNCOUT± signal from other noisy signals,

because noise on the SYNCOUT± might be interpreted as a

request for /K/ characters.

It is important to keep similar trace lengths for the CLK± and

SYSREF± signals from the clock source to each of the devices

on either end of the JESD204B links (see Figure 179). If using a

clock chip that can tightly control the phase of CLK± and

SYSREF±, the trace length matching requirements are greatly

reduced.

CLOCK SOURCE

(AD9516-1, ADCLK925)

LANE 0

LANE 1

LANE N – 1

LANE N

DEVICE CLOCK

SYSREF±

SYSREF± TRACE LENGTH

DEVICE CLOCK TRACE LENGTH

DEVICE

Figure 179. SYSREF± Signal and Device Clock Trace Length

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