AD9161BBCZ datasheet(60/144 Pages) AD

60 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 60 of 144

Configuration Parameters

The AD9161/AD9162 modes refer to the link configuration

parameters for L, K, M, N, NP, S, and F. Table 29 provides the

description and addresses for these settings.

Table 29. Configuration Parameters

JESD204B

Setting

Description

Address

L − 1

Number of lanes − 1.

Bits[4:0]

F − 1

Number of ((octets per frame) per

lane) − 1.

Bits[7:0]

K − 1

Number of frames per multiframe −

Bits[4:0]

M − 1

Number of converters − 1.

Bits[7:0]

N − 1

Converter bit resolution − 1.

Bits[4:0]

NP − 1

Bit packing per sample − 1.

Bits[4:0]

S − 1

Number of ((samples per

converter) per frame) − 1.

Bits[4:0]

High density format. Set to 1 always,

even when F does not equal 1.

Otherwise, a link configuration

error triggers and the IRQ_ILAS flag

is set.

Bit 7

DID

Device ID. Match the Device ID

sent by the transmitter.

Bits[7:0]

BID

Bank ID. Match the Bank ID sent by

the transmitter.

Bits[7:0]

LID0

Lane ID for Lane 0. Match the Lane

ID sent by the transmitter on

Logical Lane 0.

Bits[4:0]

JESDV

JESD204x version. Match the

version sent by the transmitter

(0x0 = JESD204A, 0x1 = JESD204B).

Bits[7:5]

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes are automatically

deskewed. All logical lanes are enabled or not based on the lane

number setting in Register 0x110, Bits[7:4]. The physical lanes

are all powered up by default.

To disable power to physical lanes that are not being used, set Bit x

in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0

to enable it.

JESD204B TEST MODES

PHY PRBS Testing

The JESD204B receiver on the AD9161/AD9162 includes a

PRBS pattern checker on the back end of its physical layer. This

functionality enables bit error rate (BER) testing of each

physical lane of the JESD204B link. The PHY PRBS pattern

checker does not require that the JESD204B link be established. It

can synchronize with a PRBS7, PRBS15, or PRBS31 data pattern.

PRBS pattern verification can be done on multiple lanes at once.

The error counts for failing lanes are reported for one

JESD204B lane at a time. The process for performing PRBS

testing on the AD9161/AD9162 is as follows:

1. Start sending a PRBS7, PRBS15, or PRBS31 pattern from

the JESD204B transmitter.

2. Select and write the appropriate PRBS pattern to

3. Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For example,

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

4. Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0

to 1 then back to 0.

5. Set PHY_PRBS_TEST_THRESHOLD_xBITS (Bits[23:0],

6. Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,

Bit 1). The rising edge of PHY_TEST_START starts the test.

a. (Optional) In some cases, it may be necessary to

repeat Step 4 at this point. Toggle PHY_TEST_RESET

(Register 0x316, Bit 0) from 0 to 1, then back to 0.

7. Wait 500 ms.

8. Stop the test by writing PHY_TEST_START

(Register 0x316, Bit 1) = 0.

9. Read the PRBS test results.

a. Each bit of PHY_PRBS_PASS (Register 0x31D)

corresponds to one SERDES lane (0 = fail, 1 = pass).

b. The number of PRBS errors seen on each failing lane

can be read by writing the lane number to check (0 to 7)

in PHY_SRC_ERR_CNT (Register 0x316, Bits[6:4])

and reading the PHY_PRBS_ERR_COUNT (Register

0x31C to Register 0x31A). The maximum error count

is 224−1. If all bits of Register 0x31C to Register 0x31A are

high, the maximum error count on the selected lane is

exceeded.

Table 30. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting

(Register 0x316, Bits[3:2])

PRBS Pattern

0b00 (default)

PRBS7

0b01

PRBS15

0b10

PRBS31

Transport Layer Testing

The JESD204B receiver in the AD9161/AD9162 supports the

short transport layer (STPL) test as described in the JESD204B

standard. This test can be used to verify the data mapping

between the JESD204B transmitter and receiver. To perform

this test, this function must be implemented in the logic device

and enabled there. Before running the test on the receiver side,

the link must be established and running without errors.

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