AD9161BBCZ datasheet(9/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 9 of 144

JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SERIAL INTERFACE SPEED

Guaranteed operating range

Half Rate

12.5

Gbps

Full Rate

6.25

Gbps

Oversampling

1.5

3.125

Gbps

2× Oversampling

0.750

1.5625

Gbps

SYSREF± TO DAC CLOCK TIMING SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 6.

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

8 mm × 8 mm BGA Package (AD9162BBCZ)

DC-coupled, common-mode voltage = 1.2 V

SYSREF± DIFFERENTIAL SWING = 0.4 V

Minimum Setup Time, tSYSS

163

424

Minimum Hold Time, tSYSH

160

318

SYSREF± DIFFERENTIAL SWING = 0.8 V

Minimum Setup Time, tSYSS

162

412

Minimum Hold Time, tSYSH

169

350

SYSREF± DIFFERENTIAL SWING = 1.0 V

Minimum Setup Time, tSYSS

163

376

Minimum Hold Time, tSYSH

176

354

11 mm × 11 mm BGA Package (AD9161BBCZ,

AD9162BBCAZ, AD9162BBCA)

SYSREF± DIFFERENTIAL SWING = 1.0 V

Minimum Setup Time, tSYSS

AC-coupled

117

DC-coupled, common-mode voltage = 0 V

DC-coupled, common-mode voltage = 1.25 V

129

Minimum Hold Time, tSYSH

AC-coupled

DC-coupled, common-mode voltage = 0 V

DC-coupled, common-mode voltage = 1.25 V

114

The SYSREF± pulse must be at least four DAC clock edges wide plus the setup and hold times in Table 6. For more information, see the Sync Processing Modes

Overview section.

SYSREF+

tSYSS

CLK+

tSYSH

MIN 4 DAC CLOCK EDGES

Figure 2. SYSREF± to DAC Clock Timing Diagram (Only SYSREF+ and CLK+ Shown)

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