AD9161BBCZ datasheet(57/144 Pages) AD

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Data Sheet

AD9161/AD9162

Rev. D | Page 57 of 57

The example shown in Figure 159 is demonstrated in the

following steps. Note that this example is in Subclass 1 to

achieve deterministic latency, which has a PCLK Factor

(FrameRate ÷ PCLK Rate) of 2 and uses K = 16; therefore

PCLKsPerMF = 8. This example is a hypothetical example used

to illustrate the procedure, because K is always 32 on the

AD9161/AD9162.

Calculate the minimum of all delay measurements across

all power cycles, links, and devices as follows:

MinDelay = min(all Delay values) = 4

Calculate the maximum of all delay measurements across

all power cycles, links, and devices as follows:

MaxDelay = max(all Delay values) = 9

Calculate the total delay variation (with guard band) across

all power cycles, links, and devices as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (9 + 1) − (4 − 1) = 10 − 3 = 7 PCLK cycles

Calculate the minimum delay in PCLK cycles (with guard

band) across all power cycles, links, and devices as follows:

LMFCDel

= ((MinDelay − 1) × PCLK Factor) % K

= ((4 − 1)) % 16 = (3) % 16

= 3 % 16 = 3 PCLK cycles

Write LMFCDel to Register 0x304 for all devices in the

system. Write LMFCVar to Register 0x306 for all devices in

the system.

ILAS

DATA

SYSREF±

ALIGNED DATA

LMFCRX

DYN_LINK_LATENCY

Figure 158. DYN_LINK_LATENCY_x Illustration

2345

6701

2345

DYN_LINK_LATENCY_CNT

ALIGNED DATA (LINK A)

DETERMINISTICALLY

DELAYED DATA

LMFCRX

ALIGNED DATA (LINK B)

ALIGNED DATA (LINK C)

FRAME CLOCK

LMFC

PCLK

DATA

ILAS

DATA

ILAS

DATA

ILAS

DATA

ILAS

LMFC_DELAY = 6

(FRAME CLOCK CYCLES)

LMFC_VAR = 7

(PCLK CYCLES)

Figure 159. Multilink Synchronization Settings, Derived Method Example

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