AD9161BBCZ datasheet(80/144 Pages) AD

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AD9161/AD9162

Data Sheet

Rev. D | Page 80 of 80

TEMPERATURE SENSOR

The AD9161/AD9162 has a band gap temperature sensor for

monitoring the temperature changes of the AD9161/AD9162.

The temperature must be calibrated against a known temperature

to remove the device-to-device variation on the band gap circuit

used to sense the temperature.

To calibrate, the user must take a reading at a known ambient

temperature for a single-point calibration of each

AD9161/AD9162 device. The slope for the formula is then

calculated as

M = (TREF + 190)/((CODE_REF)/1000)

where:

TREF is the temperature at which the temp sensor is read,

CODE_REF is the readback code at the measured temperature, TREF.

To monitor temperature change,

TX = TREF + M × (CODE_X − CODE_REF)/1000

where:

CODE_X is the readback code at the unknown temperature, TX.

CODE_REF is the readback code at the calibrated temperature, TREF.

To use the temperature sensor, it must be enabled by setting

Bit 0 before reading back the die temperature from Register 0x132

(LSB) and Register 0x133 (MSB).

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

The AD9161/AD9162 provide complementary current outputs,

OUTPUT+ and OUTPUT−, that sink current from an external

load that is referenced to the 2.5 V VDD25_DAC supply. Figure

189 shows an equivalent output circuit for the DAC. Compared

to most current output DACs of this type, the outputs of the

AD9161/AD9162 consist of a constant current (IFIXED), and a peak

differential ac current, ICS (ICS = ICSP + ICSN). These two currents

combine to form the IINTx currents shown in Figure 189. The

internal currents, IINTP and IINTN, are sent to the output pin and

to an input termination resistance equivalent to 100 Ω pulled to

the VDD25_DAC supply (RINT). This termination serves to divide

the output current based on the external termination resistors

that are pulled to VDD25_DAC.

ICSP

IOUTFS = 8mA – 40mA

VDD25_DAC

100Ω

OUTPUT+

OUTPUT–

100Ω

ICSN

IFIXED

IINTN

IINTP

Figure 189. Equivalent DAC Output Circuit

The example shown in Figure 189 can be modeled as a pair of

dc current sources that source a current of IOUT to each output.

This differential ac current source is used to model the signal

(that is, a digital code) dependent nature of the DAC output.

The polarity and signal dependency of this ac current source are

related to the digital code (F) by the following equation:

F (code) = (DACCODE − 32,768)/32,768

(2)

where:

−1 ≤ F (code) < +1.

DACCODE = 0 to 65,535 (decimal).

The current that is measured at the OUTPUT+ and OUTPUT−

outputs is as follows:

OUTPUT+ = (IFIXED (mA) + (F × IOUTFS)/FMAX(mA)) ×

(RINT/(RINT + RLOAD))

(3)

OUTPUT− = (IFIXED (mA) + ((FMAX − F) ×

IOUTFS)/FMAX(mA)) ×(RINT/(RINT + RLOAD))

The IFIXED value is about 3.8 mA. It is important to note that the

AD9161/AD9162 output cannot support dc coupling to the

external load, and thus must be ac-coupled through appropriately

sized capacitors for the chosen operating frequencies. Figure 190

shows the OUTPUT+ vs. DAC code transfer function when

IOUTFS is set to 40 mA.

DAC CODE

16384

32768

49152

65536

Figure 190. Gain Curve for ANA_FULL_SCALE_CURRENT[9:0] = 1023, DAC

Offset = 3.8 mA

Peak DAC Output Power Capability

The maximum peak power capability of a differential current

output DAC is dependent on its peak differential ac current,

IPEAK, and the equivalent load resistance it sees. In the case of a

1:1 balun with 100 Ω differential source termination, the equiva-

lent load that is seen by the DAC ac current source is 50 Ω. If

the AD9161/AD9162 are programmed for an IOUTFS = 40 mA, its

ideal peak ac current is 20 mA and its maximum power, delivered

to the equivalent load, is 10 × (RINT/(RINT + RLOAD)) = 8 mW, that

is, P = I2R. Because the source and load resistance seen by the

1:1 balun are equal, this power is shared equally. Therefore, the

output load receives 4 mW or 6 dBm maximum power.

To calculate the rms power delivered to the load, consider the

following:



Peak to rms of the digital waveform



Any digital backoff from digital full scale



DAC sinc response and nonideal losses in the external network

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