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AD9161BBCZ датащи(PDF) 92 Page - Analog Devices

номер детали AD9161BBCZ
подробное описание детали  11-Bit/16-Bit, 12 GSPS, RF Digital-to-Analog Converters
PDF  144 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9161BBCZ датащи(HTML) 92 Page - Analog Devices

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AD9161/AD9162
Data Sheet
Rev. D | Page 92 of 144
Hex.
Addr. Name
Bits Bit Name
Settings
Description
Reset
Access
0x006 SPI_CHIPGRADE
[7:4] PROD_GRADE
Product grade.
0x0
R
[3:0] DEV_REVISION
Device revision.
0x0
R
0x020 IRQ_ENABLE
[7:5] RESERVED
Reserved.
0x0
R
4
EN_SYSREF_JITTER
Enable SYSREF± jitter interrupt. 0x0
R/W
0 Disable interrupt.
1 Enable interrupt.
3
EN_DATA_READY
Enable JESD204x receiver ready
(JRX_DATA_READY) low
interrupt
0x0
R/W
0 Disable interrupt.
1 Enable interrupt.
2
EN_LANE_FIFO
Enable lane FIFO overflow/
underflow interrupt.
0x0
R/W
0 Disable interrupt.
1 Enable interrupt.
1
EN_PRBSQ
Enable PRBS imaginary error
interrupt.
0x0
R/W
0 Disable interrupt.
1 Enable interrupt.
0
EN_PRBSI
Enable PRBS real error interrupt 0x0
R/W
0 Disable interrupt.
1 Enable interrupt.
0x024 IRQ_STATUS
[7:5] RESERVED
Reserved.
0x0
R
4
IRQ_SYSREF_JITTER
SYSREF± jitter is too big.
Writing 1 clears the status.
0x0
R/W
3
IRQ_DATA_READY
JRX_DATA_READY is low.
Writing 1 clears the status.
0x0
R/W
0 No warning.
1 Warning detected.
2
IRQ_LANE_FIFO
Lane FIFO overflow/underflow.
Writing 1 clears the status.
0x0
R/W
0 No warning.
1 Warning detected.
1
IRQ_PRBSQ
PRBS imaginary error. Writing 1
clears the status.
0x0
R/W
0 No warning.
1 Warning detected.
0
IRQ_PRBSI
PRBS real error. Writing 1 clears
the status.
0x0
R/W
0 No warning.
1 Warning detected.
0x031 SYNC_LMFC_DELAY_FRAME
[7:5] RESERVED
Reserved.
0x0
R
[4:0] SYNC_LMFC_DELAY_SET_FRM
Desired delay from rising edge
of SYSREF± input to rising edge
of LMFC in frames.
0x0
R/W
0x032 SYNC_LMFC_DELAY0
[7:0] SYNC_LMFC_DELAY_SET[7:0]
Desired delay from rising edge
of SYSREF± input to rising edge
of LMFC in DAC clock units.
0x0
R/W
0x033 SYNC_LMFC_DELAY1
[7:4] RESERVED
Reserved.
0x0
R
[3:0] SYNC_LMFC_DELAY_SET[11:8]
Desired delay from rising edge
of SYSREF± input to rising edge
of LMFC in DAC clock units.
0x0
R/W



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