AD9161BBCZ datasheet(78/144 Pages) AD

78 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 78 of 144

Mix-Mode roll-off due to the zero-order hold at 2 × DAC clock

(see Figure 184).

–36

–33

–30

–27

–24

–21

–18

–15

–12

–9

–6

–3

1020 2040 3060 4080 5100 6120 7140 8160 9180 10200

FREQUENCY (MHz)

NRZ MODE

2× NRZ MODE

MIX-MODE

RZ MODE

Figure 184. Sinc Roll-Off with 2× NRZ Mode Added, fDAC = 5.1 GSPS

CLOCK INPUT

The AD9161/AD9162 contain a low jitter, differential clock

receiver that is capable of interfacing directly to a differential

or single-ended clock source. Because the input is self biased with a

nominal impedance of 90 Ω, it is recommended that the clock

source be ac-coupled to the CLK± input pins. The nominal

differential input is 1 V p-p, but the clock receiver can operate

with a span that ranges from 250 mV p-p to 2.0 V p-p. Better

phase noise performance is achieved with a higher clock input

level.

CLK+

TO DAC

AND DLL

CLK–

1.25V

5kΩ

40kΩ

16µA

DUTY CYCLE

RESTORER

CROSS

CONTROL

Figure 185. Clock Input

The quality of the clock source, as well as its interface to the

AD9161/AD9162 clock input, directly impacts ac performance.

Select the phase noise and spur characteristics of the clock source

to meet the target application requirements. Phase noise and

spurs at a given frequency offset on the clock source are directly

translated to the output signal. It can be shown that the phase noise

characteristics of a reconstructed output sine wave are related to

the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock

path contribution is negligible.

Figure 186 shows a clock source based on the ADF4355 low phase

noise/jitter PLL. The ADF4355 can provide output frequencies

from 54 MHz up to 6.8 GHz.

The clock control registers exist at Address 0x082 through

Address 0x084. CLK_DUTY (Register 0x082) can be used to

enable duty cycle correction (Bit 7), enable duty cycle offset

control (Bit 6), and set the duty cycle offset (Bits[4:0]). The duty

cycle offset word is a signed magnitude word, with Bit 4 being

the sign bit (1 is negative) and Bits[3:0] the magnitude. The duty

cycle adjusts across a range of approximately ±3%. Recommended

settings for this register are listed in the Start-Up Sequence

section.

The clock input has a register that adjusts the phase of the CLK+

and CLK− inputs. This register is located at Address 0x07F. The

capacitance at 20 fF per step to either the CLK+ or the CLK−

input, according to Table 41. The CLK_PHASE_TUNE register

can be used to adjust the clock input phase for better DAC

image rejection.

Table 41. CLK± Phase Adjust Values

Bits[5:0]

Capacitance at

CLK+

Capacitance at

CLK−

000000

000001

1 × 20 fF

000010

2 × 20 fF

…

011111

31 × 20 fF

100000

100001

1 × 20 fF

100010

2 × 20 fF

…

111111

31 × 20 fF

VCO

PLL

ADF4355

FREF

2GHz TO 6GHz

0dBm

100pF

7.4nH

VOUT

7.4nH

100pF

AD9161/

AD9162

CLK+

CLK–

OUTPUT

STAGE

Figure 186. Possible Signal Chain for CLK± Input

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