AD9161BBCZ datasheet(8/144 Pages) AD

8 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 8 of 144

SERIAL PORT AND CMOS PIN SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Test Comments/Conditions

Min

Typ

Max

Unit

WRITE OPERATION

See Figure 142

Maximum SCLK Clock Rate

fSCLK, 1/tSCLK

100

MHz

SCLK Clock High

tPWH

SCLK = 20 MHz

3.5

SCLK Clock Low

tPWL

SCLK = 20 MHz

SDIO to SCLK Setup Time

tDS

SCLK to SDIO Hold Time

tDH

0.5

CS to SCLK Setup Time

SCLK to CS Hold Time

0.5

READ OPERATION

See Figure 141 and Figure 142

SCLK Clock Rate

fSCLK, 1/tSCLK

MHz

SCLK Clock High

tPWH

SCLK Clock Low

tPWL

SDIO to SCLK Setup Time

tDS

SCLK to SDIO Hold Time

tDH

CS to SCLK Setup Time

SCLK to SDIO (or SDO) Data Valid Time

tDV

CS to SDIO (or SDO) Output Valid to High-Z

Not shown in Figure 141 or

Figure 142

INPUTS (SDIO, SCLK, CS, RESET, TX_ENABLE)

Voltage Input

High

VIH

1.8 V ≤ IOVDD ≤ 3.3 V

0.7 × IOVDD

Low

VIL

1.8 V ≤ IOVDD ≤ 3.3 V

0.3 × IOVDD

Current Input

High

IIH

µA

Low

IIL

−150

µA

OUTPUTS (SDIO, SDO)

Voltage Output

High

VOH

1.8 V ≤ IOVDD ≤ 3.3 V

0.8 × IOVDD

Low

VOL

1.8 V ≤ IOVDD ≤ 3.3 V

0.2 × IOVDD

Current Output

High

IOH

Low

IOL

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