AD9161BBCZ datasheet(49/144 Pages) AD

49 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 49 of 144

To enable the SERDES PLL, first set the PLL divider register (see

Table 19). Then enable the SERDES PLL by writing Register 0x280,

Bit 0 = 1. If a recalibration is needed, write Register 0x280, Bit 2 =

0b1 and then reset the bit to 0b0. The rising edge of the bit causes a

recalibration to begin.

Confirm that the SERDES PLL is working by reading

has locked. If Register 0x281, Bit 3 = 1, the SERDES PLL was

successfully calibrated. If Register 0x281, Bit 4 or Bit 5 is high, the

PLL reaches the lower or upper end of its calibration band and

must be recalibrated by writing 0 and then 1 to Register 0x280,

Bit 2.

Clock and Data Recovery

The deserializer is equipped with a CDR circuit. Instead of

recovering the clock from the JESD204B serial lanes, the CDR

recovers the clocks from the SERDES PLL. The 3 GHz to

6.25 GHz output from the SERDES PLL, shown in Figure 146, is

the input to the CDR.

A CDR sampling mode must be selected to generate the lane

rate clock inside the device. If the desired lane rate is greater

than 6.25 GHz, half rate CDR operation must be used. If the

desired lane rate is less than 6.25 GHz, disable half rate operation.

If the lane rate is less than 3 GHz, disable full rate and enable 2×

oversampling to recover the appropriate lane rate clock. Table 20

gives a breakdown of CDR sampling settings that must be set

depending on the LaneRate value.

Table 20. CDR Operating Modes

LaneRate

(Gbps)

SPI_ENHALFRATE

SPI_DIVISION_RATE,

Bits[2:1]

0.750 to 1.5625

0 (full rate)

10b (divide by 4)

1.5 to 3.125

0 (full rate)

01b (divide by 2)

3 to 6.25

0 (full rate)

00b (no divide)

6 to 12.5

1 (half rate)

00b (no divide)

The CDR circuit synchronizes the phase used to sample the data on

each serial lane independently. This independent phase adjustment

per serial interface ensures accurate data sampling and eases the

implementation of multiple serial interfaces on a PCB.

After configuring the CDR circuit, reset it and then release the

reset by writing 1 and then 0 to Register 0x206, Bit 0.

Power-Down Unused PHYs

Note that any unused and enabled lanes consume extra power

unnecessarily. Each lane that is not being used (SERDINx±)

must be powered off by writing a 1 to the corresponding bit of

PHY_PD (Register 0x201).

Equalization

To compensate for signal integrity distortions for each PHY

channel due to PCB trace length and impedance, the

AD9161/AD9162 employ an easy to use, low power equalizer

on each JESD204B channel. The AD9161/AD9162 equalizers

can compensate for insertion losses far greater than required by

the JESD204B specification. The equalizers have two modes of

operation that are determined by the EQ_POWER_MODE

(Register 0x268, Bits[7:6] = 2b’01) and operating at the maximum

lane rate of 12.5 GBPS, the equalizer can compensate for up to

11.5 dB of insertion loss. In normal mode (Register 0x268,

Bits[7:6] = 2b’00), the equalizer can compensate for up to 17.2 dB

of insertion loss. This performance is shown in Figure 147 as an

overlay to the JESD204B specification for insertion loss. Figure 147

shows the equalization performance at 12.5 Gbps, near the maxi-

mum baud rate for the AD9161/AD9162.

÷2

÷8

PCLK

GENERATOR

÷4, ÷2,

OR ÷1

CDR OVERSAMP

REG 0x289 PLL REF CLOCK

VALID RANGE

35MHz TO 80MHz

SAMPLE CLOCK

I, Q TO CDR

VALID RANGE

3GHz TO 6.25GHz

ENABLE HALF RATE

DIVISION RATE

REG 0x230

JESD LANE CLOCK

(SAME RATE AS PCLK)

INTERPOLATION

JESD LANES

REG 0x110

PLL_REF_CLK_RATE

1×, 2×, 4×

REG 0x084

DAC CLOCK

(5GHz)

÷6 TO ÷127,

DEFAULT: 10

CDR

÷N

÷4

MODE

HALF RATE

FULL RATE, NO DIV

FULL RATE, DIV 2

FULL RATE, DIV 4

DIVIDE (N)

160

Figure 146. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

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